SAA7108AE PHILIPS [NXP Semiconductors], SAA7108AE Datasheet - Page 128

• Manufacturer Part Number: SAA7108AE
• Description: HD-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 110 Subaddresses 93H and 94H
Table 111 Subaddresses 95H and 96H
Table 112 Subaddress 96H
Table 113 Subaddress 97H
2004 Jun 29
YOFSE
YPIX
EFS
PCBN
SLAVE
ILC
YFIL
HFS
VFS
OFS
PFS
OVS
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
HD-CODEC
vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually,
YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing
defines the number of requested input lines from the feeding device;
number of requested lines = YPIX + YOFSE
LOGIC
LEVEL
LOGIC
LEVEL
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
frame sync signal at pin FSVGC ignored in slave mode
frame sync signal at pin FSVGC accepted in slave mode
normal polarity of CBO signal (HIGH during active video)
inverted polarity of CBO signal (LOW during active video)
the SAA7108AE; SAA7109AE is timing master to the graphics controller
the SAA7108AE; SAA7109AE is timing slave to the graphics controller
if hardware cursor insertion is active, set LOW for non-interlaced input signals
if hardware cursor insertion is active, set HIGH for interlaced input signals
luminance sharpness booster disabled
luminance sharpness booster enabled
horizontal sync is directly derived from input signal (slave mode) at pin HSVGC
horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if
EFS is set HIGH)
vertical sync (field sync) is directly derived from input signal (slave mode) at
pin VSVGC
vertical sync (field sync) is derived from a frame sync signal (slave mode) at
pin FSVGC (only if EFS is set HIGH)
pin FSVGC is switched to input
pin FSVGC is switched to active output
polarity of signal at pin FSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
polarity of signal at pin FSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
pin VSVGC is switched to input
pin VSVGC is switched to active output
128
DESCRIPTION
DESCRIPTION
YOFSO
DESCRIPTION
DESCRIPTION
SAA7108AE; SAA7109AE
Product specification