SAA7108AE PHILIPS [NXP Semiconductors], SAA7108AE Datasheet - Page 78

• Manufacturer Part Number: SAA7108AE
• Description: HD-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9.6.2
Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for
channel-select. The frequencies of these signals are defined by the parameters:
See Table 36 for examples.
Table 36 Programming examples for ASCLK/ALRCLK clock generation
9.6.3
Further control signals are available to define reference clock edges and vertical references; see Table 37.
Table 37 Control signals
2004 Jun 29
APLL[3AH[3]]
AMVR[3AH[2]] Audio Master clock Vertical Reference:
LRPH[3AH[1]]
SCPH[3AH[0]]
SDIV[5:0] 38H[5:0] according to the equation:
LRDIV[5:0] 39H[5:0] according to the equation:
HD-CODEC
CONTROL
AMXCLK
SIGNAL
11.2896
12.288
(MHz)
8.192
S
O
IGNALS
THER CONTROL SIGNALS
ASCLK
Audio PLL mode:
ALRCLK Phase:
ASCLK Phase:
0: PLL closed
1: PLL open
0: internal vertical reference
1: external vertical reference
0: invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK
1: do not invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK
0: invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK
1: do not invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK
ASCLK
1411.2
2822.4
(kHz)
1536
1024
2048
768
AND
ALRCLK
DECIMAL
3
7
3
1
3
1
SDIV
f
ASCLK
f
ALRCLK
=
HEX
03
07
03
01
03
01
78
=
------------------------------------- -
SDIV
DESCRIPTION
-------------------------- -
LRDIV 2
f
AMXCLK
f
ASCLK
+
1
ALRCLK
2
(kHz)
44.1
48
32
LRDIV[5:0]
SAA7108AE; SAA7109AE
SDIV[5:0]
=
DECIMAL
=
---------------------- -
2f
f
------------------- - 1
2f
f
AMXCLK
16
16
32
16
32
ASCLK
ALRCLK
8
ASCLK
Product specification
LRDIV
–
HEX
10
08
10
10
10
10