SAA7108AE PHILIPS [NXP Semiconductors], SAA7108AE Datasheet - Page 61

• Manufacturer Part Number: SAA7108AE
• Description: HD-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9.3.2
The overall horizontal scaling factor has to be split into a
binary and a rational value according to the following
equation:
where, the parameter of the prescaler XPSC[5:0] = 1 to 63
and the parameter of VPD phase interpolation
XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical
values). For example,
binary factor is processed by the prescaler, the arbitrary
non-integer ratio is achieved via the variable phase delay
VPD circuitry, called horizontal fine scaling. The latter
calculates horizontally interpolated new samples with a
6-bit phase accuracy, which relates to less than 1 ns jitter
for regular sampling schemes. Together the prescaler and
fine scaler form the horizontal scaler of the SAA7108AE;
SAA7109AE.
Using the accumulation length function of the prescaler
(XACL[5:0] A1H[5:0]), application and destination
dependent (e.g. scale for display or for a compression
machine), a compromise between visible bandwidth and
alias suppression can be found.
9.3.2.1
The prescaling function consists of an FIR anti-alias filter
stage and an integer prescaler, which together form an
adaptive prescale dependent low-pass filter to balance the
sharpness and aliasing effects.
The FIR pre-filter stage implements different low-pass
characteristics to reduce the anti-alias for downscales in
the range of 1 to
reduces artefacts for CIF output formats (to be used in
combination with the prescaler set to
Table 24.
The function of the prescaler is defined by:
2004 Jun 29
H scale ratio
An integer prescaling ratio XPSC[5:0] A0H[5:0] (equals
1 to 63), which covers the integer downscale range
1 to
An averaging sequence length XACL[5:0] A1H[5:0]
(equals 0 to 63); range 1 to 64
A DC gain renormalization XDCG[2:0] A2H[2:0];
1 down to
HD-CODEC
1
63
H
H scale ratio
ORIZONTAL SCALING
Horizontal prescaler (subaddresses
A0H to A7H and D0H to D7H)
1
=
128
--------------------------- -
XPSC[5:0]
1
)
2
. A CIF optimized filter is built-in, which
1
1
3.5
=
output pixel
----------------------------- -
is split into
input pixel
------------------------------ -
XSCY[12:0]
1024
1
1
2
4
scale); see
1.14286. The
61
The prescaler creates a prescale dependent FIR low-pass,
with up to 64 + 7 filter taps. The parameter XACL[5:0] can
be used to vary the low-pass characteristic for a given
integer prescale of
decide between signal bandwidth (sharpness impression)
and alias.
The equation for the XPSC[5:0] calculation is:
Where:
The use of the prescaler results in a XACL[5:0] and
XC2_1 dependent gain amplification. The amplification
can be calculated according to the equation:
DC gain = [(XACL[5:0]
It is recommended to use sequence lengths and weights,
which results in a 2
amplitudes can be renormalized by the XDCG[2:0]
controlled
The renormalization range of XDCG[2:0] is 1,
to
Other amplifications have to be normalized by using the
following BCS control circuitry. In these cases the
prescaler has to be set to an overall gain 1, e.g. for an
accumulation sequence of ‘1 + 1 + 1’ (XACL[5:0] = 2 and
XC2_1 = 0), XDCG[2:0] must be set to ‘010’, which
equals
(SATN[7:0] and CONT[7:0] value = lower integer of
4
The use of XACL[5:0] is XPSC[5:0] dependent.
XACL[5:0] must be <2
XACL[5:0] can be used to find a compromise between
bandwidth (sharpness) and alias effects.
XPSC[5:0]
3
The bit XC2_1[A2H[3]], which defines the weighting of
the incoming pixels during the averaging process
– XC2_1 = 0
– XC2_1 = 1
the range is 1 to 63 (value 0 is not allowed);
Npix_in = number of input pixel, and
Npix_out = number of desired output pixel over the
complete horizontal scaler.
1
128
64).
.
1
4
and the BCS has to amplify the signal to
------
2
1
=
N
lower integer of
shifter of the prescaler.
SAA7108AE; SAA7109AE
1
N
1 + 1...+ 1 + 1
1 + 2...+ 2 + 1.
XPSC[5:0]
DC gain amplification, as these
XC2_1) + 1]
XPSC[5:0].
. The user can therewith
---------------------- -
Npix_out
Npix_in
Product specification
(XC2_1 + 1)
1
2
... down
4
3