XC4VFX140 XILINX [Xilinx, Inc], XC4VFX140 Datasheet
XC4VFX140
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XC4VFX140 Summary of contents
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R DS123 (v2.9) May 09, 2006 Features • In-System Programmable PROMs for Configuration of Xilinx FPGAs • Low-Power Advanced CMOS NOR FLASH Process • Endurance of 20,000 Program/Erase Cycles • Operation over Full Industrial Temperature Range (–40°C to +85°C) • ...
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R CLK TCK Control TMS and JTAG TDI Interface TDO CF Figure 1: XCFxxS Platform Flash PROM Block Diagram FI CLK CE OSC Control TCK and TMS TDI JTAG TDO Interface CF Figure 2: XCFxxP Platform Flash PROM Block Diagram ...
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... XC4VLX80 23,291,008 XC4VLX100 30,711,680 XC4VLX160 40,347,008 XC4VLX200 51,367,808 Virtex-4 FX XC4VFX12 4,765,568 XC4VFX20 7,242,624 XC4VFX40 14,936,192 XC4VFX60 21,002,880 XC4VFX100 33,065,408 XC4VFX140 47,856,896 Virtex-4 SX XC4VSX25 9,147,648 XC4VSX35 13,700,288 XC4VSX55 22,749,184 Virtex-II Pro X XC2VPX20 8,214,560 XC2VPX70 26,098,976 Virtex-II Pro XC2VP2 1,305,376 XC2VP4 3,006,496 XC2VP7 ...
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R Table 2: Xilinx FPGAs and Compatible Platform Flash PROMs (Continued) Configuration FPGA Platform Flash PROM Bitstream XC3S1200E 3,832,320 XC3S1600E 5,957,760 Spartan-3L XC3S1000L 3,223,488 XC3S1500L 5,214,784 XC3S5000L 13,271,936 Spartan-3 XC3S50 439,264 XC3S200 1,047,616 XC3S400 1,699,136 XC3S1000 3,223,488 XC3S1500 5,214,784 XC3S2000 ...
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R Reliability and Endurance Xilinx in-system programmable products provide a guaranteed endurance level of 20,000 in-system program/erase cycles and a minimum data retention of 20 years. Each device meets all functional, performance, and data retention specifications within this endurance limit. ...
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R logic 0. IR[2] is unused, and is set to '0'. The remaining bits IR[1:0] are set to '01' as defined by IEEE Std. 1149.1. XCFxxP Instruction Register (16 bits wide) The Instruction Register (IR) for the XCFxxP PROM is ...
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R Boundary Scan Register The boundary-scan register is used to control and observe the state of the device pins during the EXTEST, SAMPLE/PRELOAD, and CLAMP instructions. Each output pin on the Platform Flash PROM has two register stages which contribute ...
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R T CKMIN TCK TMS TDI TDO TAP AC Parameters Table 10 shows the timing parameters for the TAP waveforms shown in Table 10: Test Access Port Timing Parameters Symbol T TCK minimum clock period when V CKMIN T TMS ...
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R When the FPGA deasserts BUSY, indicating that it is ready to receive additional configuration data, the PROM will begin driving new data onto the configuration interface. Decompression The 8/16/32 Mbit XCFxxP Platform Flash PROMs include a built-in data decompressor ...
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R PROM 0 REV 0 (8 Mbits) REV 1 (8 Mbits) REV 2 (8 Mbits) REV 3 (8 Mbits) 4 Design Revisions (a) Design Revision storage examples for a single XCF32P PROM PROM 0 REV 0 (16 Mbits) REV 1 ...
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slow default frequency. The FPGA’s bitstream contains configuration bits which can switch CCLK to a higher frequency for the remainder of the Master Serial configuration sequence. The desired CCLK frequency is selected during bitstream generation. Connecting the ...
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R internally generated CCLK signal. If BUSY is asserted (High) by the FPGA, the configuration data must be held until BUSY goes Low. An external data source or external pull-down resistors must be used to enable the FPGA's active Low ...
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R • The PROM CF pin is typically connected to the FPGA's PROG_B (or PROGRAM) input. For the XCFxxP only, the CF pin is a bidirectional pin. If the XCFxxP CF pin is not connected to the FPGA's PROG_B (or ...
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R Configuration PROM to FPGA Device Interface Connection Diagrams CCJ CCO CCINT V CCINT (2) V CCO (2) V CCJ Platform Flash PROM OE/RESET TDI TDI TMS TMS TCK TCK TDO GND Notes: 1 For Mode pin ...
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R (3) External Oscillator CCJ CCO CCINT V CCINT (2) V CCO (2) V CCJ Platform Flash PROM OE/RESET TDI TDI TMS TMS TCK TCK TDO GND Notes: 1 For Mode pin connections and DONE pin pull-up ...
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CCJ CCO CCINT CCJ V D0 CCINT (2) V CCO (2) V CCJ Platform Flash PROM Cascaded CLK PROM CE (PROM 1) CEO OE/RESET (3) TDI TDI CF TMS TMS TCK TCK TDO TDO GND ...
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CCJ CCO CCINT V CCINT (2) V CCO (2) V CCJ XCFxxP Platform Flash PROM OE/RESET TDI TDI TMS TMS BUSY TCK TCK TDO GND Notes: 1 For Mode pin connections and DONE pin pull-up value, ...
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R (5) External Oscillator CCJ CCO CCINT V CCINT (2) V CCO (2) V CCJ XCFxxP Platform Flash PROM OE/RESET TDI TDI TMS TMS BUSY TCK TCK TDO GND Notes: 1 For Mode pin connections and DONE ...
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CCJ CCO CCINT CCJ CCO V D[0:7] CCINT (2) V CCO (2) V CCJ XCFxxP Platform Flash PROM Cascaded CLK PROM CE (PROM 1) CEO OE/RESET (5) TDI TDI CF (4) TMS TMS BUSY ...
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CCJ CCO CCINT CCJ (3) External Oscillator D0 V CCINT (2) V CCO (2) V CCJ XCFxxP Platform Flash PROM (3) Cascaded CLK PROM CE (PROM 1) CEO OE/RESET (4) TDI TDI CF TMS TMS ...
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CCJ CCO CCINT CCJ (5) External Oscillator V D[0:7] CCINT (2) V CCO (2) V CCJ XCFxxP Platform Flash PROM (5) Cascaded CLK PROM CE (PROM 1) CEO OE/RESET (6) TDI TDI CF (4) ...
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R Reset and Power-On Reset Activation At power up, the device requires the V monotonically rise to the nominal operating voltage within the specified V rise time. If the power supply cannot CCINT meet this requirement, then the device might ...
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R pull-up resistor is used, but refer to the appropriate FPGA data sheet for the recommended DONE pin pull-up value. If the DONE circuit is connected to an LED to indicate FPGA configuration is complete, and is also connected to ...
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R DC Electrical Characteristics Absolute Maximum Ratings Symbol Description V Internal supply voltage relative to GND CCINT V I/O supply voltage relative to GND CCO V JTAG I/O supply voltage relative to GND CCJ V Input voltage with respect to ...
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R Recommended Operating Conditions Symbol Description V Internal voltage supply CCINT V 3.3V Operation CCO Supply voltage 2.5V Operation for output 1.8V Operation drivers 1.5V Operation V 3.3V Operation Supply voltage CCJ for JTAG output 2.5V Operation drivers V 3.3V ...
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R DC Characteristics Over Operating Conditions Symbol Description High-level output voltage for 3.3V outputs High-level output voltage for 2.5V outputs V OH High-level output voltage for 1.8V outputs High-level output voltage for 1.5V outputs Low-level output voltage for 3.3V outputs ...
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R AC Electrical Characteristics AC Characteristics Over Operating Conditions XCFxxS and XCFxxP PROM as Configuration Slave with CLK Input Pin as Clock Source T SCE CE OE/RESET CLK BUSY T OE (optional DATA HCF CF ...
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R Symbol Description CE or OE/RESET to data float delay when V = 3.3V or 2.5V CCO OE/RESET to data float delay when V = 1.8V CCO (6) Clock period (serial mode) when V (6) Clock ...
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R Symbol Description REV_SEL hold time from CF OE/RESET when V = 3.3V or 2.5V CCO T HRV REV_SEL hold time from CF OE/RESET (8) when V = 1.8V CCO Notes test load = ...
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R XCFxxP PROM as Configuration Master with CLK Input Pin as Clock Source CE OE/RESET CLK CLKOUT T CECC T OECC BUSY T OE (optional DATA CFCC T HCF CF EN_EXT_SEL T T SXT HXT ...
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R Symbol (7) Clock period (serial mode) when V (7) Clock period (serial mode) when V T CYCO (7) Clock period (parallel mode) when V (7) Clock period (parallel mode) when V (3) CLK Low time when ...
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R Symbol EN_EXT_SEL hold time from CF, CE, or OE/RESET when V T HXT EN_EXT_SEL hold time from CF, CE, or OE/RESET when V REV_SEL setup time to CF, CE, or OE/RESET when V T SRV REV_SEL setup time to ...
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R XCFxxP PROM as Configuration Master with Internal Oscillator as Clock Source CE OE/RESET CLKOUT T CEC T OEC BUSY T OE (optional DATA CFC T HCF CF EN_EXT_SEL T T SXT HXT T T ...
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R Symbol OE/RESET hold time (guarantees counters are reset) T HOE OE/RESET hold time (guarantees counters are reset) BUSY setup time to CLKOUT when BUSY setup time to CLKOUT when V BUSY hold time to CLKOUT when ...
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R Symbol CLKOUT alternate (slower) frequency F S CLKOUT alternate (slower) frequency with decompression Notes test load = 50 pF for XCF01S/XCF02S/XCF04S for XCF08P/XCF16P/XCF32P. 2. Float delays are measured with loads. Transition is ...
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R AC Characteristics Over Operating Conditions When Cascading OE/RESET CE CLK CLKOUT (optional) DATA CEO Symbol Description CLK to output float delay when V = 2.5V or 3.3V T CCO CDF CLK to output float delay (3,5) CLK to CEO ...
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R Pinouts and Pin Descriptions The XCFxxS Platform Flash PROM is available in the VO20 and VOG20 packages. The XCFxxP Platform Flash PROM is available in the VO48, VOG48, FS48, and FSG48 packages. Notes: 1. VO20/VOG20 denotes a 20-pin (TSSOP) ...
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R Table 13: XCFxxS Pin Names and Descriptions Boundary Boundary Scan Pin Name Scan Order Function VCCO VCCJ GND DNC XCFxxS VO20/VOG20 Pinout Diagram (DNC) 3 CLK 4 TDI VO20/VOG20 5 TMS Top View TCK 6 CF ...
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R XCFxxP Pinouts and Pin Descriptions VXCFxxP O48/VOG48 and FS48/FSG48 Pin Names and Descriptions Table 14 provides a list of the pin names and descriptions for the XCFxxP 48-pin VO48/VOG48 and 48-pin FS48/FSG48 packages. Table 14: XCFxxP Pin Names and ...
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R Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Continued) Boundary Boundary Pin Name Scan Scan Order Function 06 Data Out 05 Output Enable CEO 31 Data In EN_EXT_SEL REV_SEL0 30 Data In 29 Data In REV_SEL1 12 ...
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R Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Continued) Boundary Boundary Pin Name Scan Scan Order Function VCCO VCCJ GND DNC XCFxxP VO48/VOG48 Pinout Diagram DNC 1 GND 2 DNC 3 VCCINT 4 BUSY ...
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R XCFxxP FS48/FSG48 Pin Names Table 15: XCFxxP Pin Names (FS48/FSG48) Pin Pin Pin Name Number Number A1 GND E1 A2 GND E2 A3 OE/RESET E3 A4 DNC VCCINT F1 B2 VCCO ...
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R Ordering Information Device Number XCF01S Package Type XCF02S VO20 = 20-pin TSSOP Package XCF04S VOG20 = 20-pin TSSOP Package, Pb-free Device Number XCF08P Package Type XCF16P VO48 = 48-pin TSOP Package XCF32P VOG48 = 48-pin TSOP Package, Pb-free FS48 ...
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R Revision History The following table shows the revision history for this document. Date Version 04/29/03 1.0 Xilinx Initial Release. 06/03/03 1.1 Made edits to all pages. 11/05/03 2.0 Major revision. 11/18/03 2.1 Pinout corrections as follows: • • • ...
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R • Added Pb-free package options VOG20, FSG48, and VOG48. 07/20/04 2.4 • • Section • • 10/18/04 2.5 • • • Table • Table • Table • Table • Added Virtex-4 LX/FX/SX configuration data to 03/14/05 2.6 • Corrected ...
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R • Update to the first paragraph of 12/29/05 2.8 • Added JTAG cautionary note to • Corrected logic values for Erase/Program (ER/PROG) Status field, IR[4], listed under • Sections • Notes for • Enhanced description under section • Enhanced ...