XC4VFX140 XILINX [Xilinx, Inc], XC4VFX140 Datasheet - Page 18

• Manufacturer Part Number: XC4VFX140
• Description: Platform Flash In-System Programmable Configuration PROMS
• Manufacturer: XILINX [Xilinx, Inc]

DS123 (v2.9) May 09, 2006
TMS
TDO
TCK
TDI
V
CCJ
R
V
CCO
V
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down externally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high-
5 In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or, optionally, the
6 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it must be
CCINT
frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal
is used, then CLKOUT must be tied to a 4.7 KΩ resistor pulled up to V
tied to V
V
V
V
TDI
TMS
TCK
GND
CCINT
CCO
CCJ
XCFxxP
Platform Flash
PROM
CCO
(2)
(2)
External
Oscillator
via a 4.7 kΩ pull-up resistor.
OE/RESET
(5)
BUSY
Figure 10: Configuring in Slave SelectMAP Mode
CLK
D[0:7]
CF
CEO
TDO
CE
(5)
(6)
(4)
V
CCO
(2)
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMS
(1)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
GND
Xilinx FPGA
Slave SelectMAP
CCO
(4)
.
MODE PINS
RDWR_B
CS_B
TDO
(1)
1KΩ
PROG_B
BUSY
1KΩ
INIT_B
DONE
D[0:7]
CCLK
(4)
I/O
I/O
...OPTIONAL
Slave FPGAs
with identical
configurations
(3)
(3)
ds123_15_122105
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