XC4VFX140 XILINX [Xilinx, Inc], XC4VFX140 Datasheet - Page 6

• Manufacturer Part Number: XC4VFX140
• Description: Platform Flash In-System Programmable Configuration PROMS
• Manufacturer: XILINX [Xilinx, Inc]

logic 0. IR[2] is unused, and is set to '0'. The remaining bits
IR[1:0] are set to '01' as defined by IEEE Std. 1149.1.
XCFxxP Instruction Register (16 bits wide)
The Instruction Register (IR) for the XCFxxP PROM is sixteen
bits wide and is connected between TDI and TDO during an
instruction scan sequence. The detailed composition of the
instruction capture pattern is illustrated in
The instruction capture pattern shifted out of the XCFxxP
device includes IR[15:0]. IR[15:9] are reserved bits and are
set to a logic 0. The ISC Error field, IR[8:7], contains a 10
when an ISC operation is a success; otherwise a 01 when
an In-System Configuration (ISC) operation fails. The
Table 6: Platform Flash PROM Boundary Scan Instructions
Table 7: XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
Table 8: XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
DS123 (v2.9) May 09, 2006
Notes:
1.
Required Instructions
BYPASS
SAMPLE/PRELOAD
EXTEST
CLAMP
HIGHZ
IDCODE
USERCODE
Platform Flash PROM
Specific Instructions
CONFIG
Optional Instructions
Boundary-Scan Command
TDI →
TDI →
For more information see
R
Reserved
IR[15:9]
Reserved
IR[7:5]
"Initiating FPGA Configuration," page
ISC Error
IR[8:7]
XCFxxS IR[7:0]
ISC Status
(hex)
FF
01
00
FA
FC
FE
FD
EE
Table 8, page
IR[4]
ER/PROG
IR[6:5]
Error
XCFxxP IR[15:0]
6.
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Platform Flash In-System Programmable Configuration PROMS
ER/PROG
Security
(hex)
FFFF
0001
0000
00FA
00FC
00FE
00FD
00EE
Status
13.
IR[4]
IR[3]
Erase/Program (ER/PROG) Error field, IR[6:5], contains a
10 when an erase or program operation is a success;
otherwise a 01 when an erase or program operation fails.
The Erase/Program (ER/PROG) Status field, IR[4], contains
a logic 0 when the device is busy performing an erase or
programming operation; otherwise, it contains a logic 1. The
ISC Status field, IR[3], contains logic 1 if the device is
currently in In-System Configuration (ISC) mode; otherwise,
it contains logic 0. The DONE field, IR[2], contains logic 1 if
the sampled design revision has been successfully
programmed; otherwise, a logic 0 indicates incomplete
programming. The remaining bits IR[1:0] are set to 01 as
defined by IEEE Std. 1149.1.
ISC Status
Enables BYPASS
Enables boundary-scan SAMPLE/PRELOAD operation
Enables boundary-scan EXTEST operation
Enables boundary-scan CLAMP operation
Places all outputs in high-impedance state
simultaneously
Enables shifting out 32-bit IDCODE
Enables shifting out 32-bit USERCODE
Initiates FPGA configuration by pulsing CF pin Low
once. (For the XCFxxP this command also resets the
selected design revision based on either the external
REV_SEL[1:0] pins or on the internal design revision
selection bits.)
IR[3]
IR[2]
0
(1)
Instruction Description
DONE
IR[2]
IR[1:0]
0 1
IR[1:0]
0 1
→ TDO
→ TDO
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