XC4VFX140 XILINX [Xilinx, Inc], XC4VFX140 Datasheet - Page 39

• Manufacturer Part Number: XC4VFX140
• Description: Platform Flash In-System Programmable Configuration PROMS
• Manufacturer: XILINX [Xilinx, Inc]

XCFxxP Pinouts and Pin Descriptions
VXCFxxP O48/VOG48 and FS48/FSG48 Pin Names and Descriptions
Table 14
packages.
Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48)
DS123 (v2.9) May 09, 2006
D0
D1
D2
D3
D4
D5
D6
D7
CLK
OE/RESET
CE
CF
Pin Name
provides a list of the pin names and descriptions for the XCFxxP 48-pin VO48/VOG48 and 48-pin FS48/FSG48
R
Scan Order
Boundary
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
01
04
03
02
00
11
10
09
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Boundary
Function
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data In
Data In
Data In
Data In
Scan
D0 is the DATA output pin to provide data for configuring an
FPGA in serial mode.
D0-D7 are the DATA output pins to provide parallel data for
configuring a Xilinx FPGA in SelectMap (parallel) mode.
The D0 output is set to a high-impedance state during ISPEN
(when not clamped).
The D1-D7 outputs are set to a high-impedance state during
ISPEN (when not clamped) and when serial mode is selected
for configuration. The D1-D7 pins can be left unconnected
when the PROM is used in serial mode.
Configuration Clock Input. An internal programmable control
bit selects between the internal oscillator and the CLK input
pin as the clock source to control the configuration sequence.
Each rising edge on the CLK input increments the internal
address counter if the CLK input is selected, CE is Low,
OE/RESET is High, BUSY is Low (parallel mode only), and
CF is High.
Output Enable/Reset (Open-Drain I/O).
When Low, this input holds the address counter reset and the
DATA and CLKOUT outputs are placed in a high-impedance
state. This is a bidirectional open-drain pin that is held Low
while the PROM completes the internal power-on reset
sequence. Polarity is not programmable.
Chip Enable Input. When CE is High, the device is put into
low-power standby mode, the address counter is reset, and
the DATA and CLKOUT outputs are placed in a
high-impedance state.
Configuration Pulse (Open-Drain I/O). As an output, this pin
allows the JTAG CONFIG instruction to initiate FPGA
configuration without powering down the FPGA. This is an
open-drain signal that is pulsed Low by the JTAG CONFIG
command. As an input, on the rising edge of CF, the current
design revision selection is sampled and the internal address
counter is reset to the start address for the selected revision.
If unused, the CF pin must be pulled High using an external
4.7 KΩ pull-up to V
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMS
CCO
Pin Description
.
VOG48)
(VO48/
48-pin
TSOP
28
29
32
33
43
44
47
48
12
11
13
6
TFBGA
FSG48)
48-pin
(FS48/
H6
H5
E5
D5
C5
B5
A5
A6
B3
A3
B4
D1
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