XC4VFX140 XILINX [Xilinx, Inc], XC4VFX140 Datasheet - Page 7

• Manufacturer Part Number: XC4VFX140
• Description: Platform Flash In-System Programmable Configuration PROMS
• Manufacturer: XILINX [Xilinx, Inc]

Boundary Scan Register
The boundary-scan register is used to control and observe
the state of the device pins during the EXTEST,
SAMPLE/PRELOAD, and CLAMP instructions. Each output
pin on the Platform Flash PROM has two register stages
which contribute to the boundary-scan register, while each
input pin has only one register stage. The bidirectional pins
have a total of three register stages which contribute to the
boundary-scan register. For each output pin, the register
stage nearest to TDI controls and observes the output state,
and the second stage closest to TDO controls and observes
the High-Z enable state of the output pin. For each input pin,
a single register stage controls and observes the input state
of the pin. The bidirectional pin combines the three bits, the
input stage bit is first, followed by the output stage bit and
finally the output enable stage bit. The output enable stage
bit is closest to TDO.
See the XCFxxS/XCFxxP Pin Names and Descriptions
Tables in the
section for the boundary-scan bit order for all connected
device pins, or see the appropriate BSDL file for the
complete boundary-scan bit order description under the
"attribute BOUNDARY_REGISTER" section in the BSDL
file. The bit assigned to boundary-scan cell 0 is the LSB in
the boundary-scan register, and is the register bit closest to
TDO.
Identification Registers
IDCODE Register
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be shifted out for
examination by using the IDCODE instruction. The IDCODE
is available to any other system component via JTAG.
Table 9
Flash PROMs.
Table 9: IDCODES Assigned to Platform Flash PROMs
DS123 (v2.9) May 09, 2006
Notes:
1.
The <v> in the IDCODE field represents the device’s revision
code (in hex) and may vary.
lists the IDCODE register values for the Platform
XCF01S
XCF02S
XCF04S
XCF08P
XCF16P
XCF32P
R
Device
"Pinouts and Pin Descriptions," page 37
IDCODE
<v>5044093
<v>5045093
<v>5046093
<v>5057093
<v>5058093
<v>5059093
(1)
(hex)
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Platform Flash In-System Programmable Configuration PROMS
The IDCODE register has the following binary format:
where
v = the die version number
f = the PROM family code
a = the specific Platform Flash PROM product ID
c = the Xilinx manufacturer's ID
The LSB of the IDCODE register is always read as logic 1
as defined by IEEE Std. 1149.1.
USERCODE Register
The USERCODE instruction gives access to a 32-bit user
programmable scratch pad typically used to supply
information about the device's programmed contents. By
using the USERCODE instruction, a user-programmable
identification code can be shifted out for examination. This
code is loaded into the USERCODE register during
programming of the Platform Flash PROM. If the device is
blank or was not loaded during programming, the
USERCODE register contains FFFFFFFFh.
Customer Code Register
For the XCFxxP Platform Flash PROM, in addition to the
USERCODE, a unique 32-byte Customer Code can be
assigned to each design revision enabled for the PROM.
The Customer Code is set during programming, and is
typically used to supply information about the design
revision contents. A private JTAG instruction is required to
read the Customer Code. If the PROM is blank, or the
Customer Code for the selected design revision was not
loaded during programming, or if the particular design
revision is erased, the Customer Code will contain all ones.
Platform Flash PROM TAP
Characteristics
The Platform Flash PROM family performs both in-system
programming and IEEE 1149.1 boundary-scan (JTAG)
testing via a single 4-wire Test Access Port (TAP). This
simplifies system designs and allows standard Automatic
Test Equipment to perform both functions. The AC
characteristics of the Platform Flash PROM TAP are
described as follows.
TAP Timing
Figure 4, page 8
signals. These TAP timing characteristics are identical for
both boundary-scan and ISP operations.
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
shows the timing relationships of the TAP
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