XC4VFX140 XILINX [Xilinx, Inc], XC4VFX140 Datasheet - Page 19

• Manufacturer Part Number: XC4VFX140
• Description: Platform Flash In-System Programmable Configuration PROMS
• Manufacturer: XILINX [Xilinx, Inc]

TMS
TDO
TCK
DS123 (v2.9) May 09, 2006
TDI
V
CCJ
V
CCO
V
Figure 11: Configuring Multiple Devices with Identical Patterns in Master/Slave SelectMAP Mode
CCINT
R
V
V
V
TDI
TMS
TCK
GND
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high-
5 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it must be tied to
CCINT
CCO
CCJ
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
V CCO via a 4.7 kΩ pull-up resistor.
(2)
(2)
OE/RESET
BUSY
D[0:7]
CF
CEO
TDO
CLK
CE
(5)
(4)
V
CCJ
V
CCO
V
CCINT
V
V
V
TDI
TMS
TCK
GND
CCINT
CCO
CCJ
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
(2)
(2)
OE/RESET
BUSY
D[0:7]
CF
CEO
TDO
CLK
CE
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Platform Flash In-System Programmable Configuration PROMS
(5)
(4)
V
CCO
(2)
(1)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
GND
Xilinx FPGA
Master SelectMAP
(4)
MODE PINS
RDWR_B
CS_B
TDO
(1)
I/O
I/O
(3)
(3)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
GND
Xilinx FPGA
Slave SelectMAP
(4)
MODE PINS
RDWR_B
CS_B
TDO
(1)
ds123_16_122105
I/O
I/O
19
(3)
(3)