KSZ8864RMNI MICREL [Micrel Semiconductor], KSZ8864RMNI Datasheet
KSZ8864RMNI
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KSZ8864RMNI Summary of contents
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General Description The KSZ8864RMN is a highly-integrated, Layer 2 managed 4-port switch with optimized design, plentiful features and smallest package size designed for cost-sensitive 10/100Mbps 4-port switch systems with on-chip termination, lowest-power consumption, and small package to save ...
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Features Advanced Switch Features IEEE 802.1q VLAN support for up to 128 VLAN groups (full-range 4096 of VLAN IDs). Static MAC table supports entries. VLAN ID tag/untag options, per port basis. IEEE 802.1p/q ...
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... Applications Typical VoIP Phone Set-top/Game Box Automotive Industrial Control IPTV POF Ordering Information Part Number Temperature Range ° KSZ8864RMN 40 KSZ8864RMNI ° Revision History Revision 1.0 10/29/10 1.1 12/16/10 1.2 01/20/11 1.3 03/18/11 1.4 07/28/11 September 2011 SOHO Residential Gateway Broadband Gateway / Firewall / VPN ...
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Contents Pin Configuration ..........................................................................................................................................................13 Pin Description ..............................................................................................................................................................14 Pin for Strap-in Options................................................................................................................................................19 Introduction ...................................................................................................................................................................22 Functional Overview: Physical Layer Transceiver ....................................................................................................22 100BASE-TX Transmit ...............................................................................................................................................22 100BASE-TX Receive ................................................................................................................................................22 PLL Clock Synthesizer................................................................................................................................................22 Scrambler/De-Scrambler (100BASE-TX only)............................................................................................................23 10BASE-T Transmit ....................................................................................................................................................23 10BASE-T Receive .....................................................................................................................................................23 MDI/MDI-X Auto Crossover ...
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Port-Based Priority..................................................................................................................................................36 802.1p-Based Priority .............................................................................................................................................36 DiffServ-Based Priority ...........................................................................................................................................37 Spanning Tree Support...............................................................................................................................................37 Rapid Spanning Tree Support ....................................................................................................................................38 Tail Tagging Mode ......................................................................................................................................................39 IGMP Support .............................................................................................................................................................40 Port Mirroring Support ................................................................................................................................................40 VLAN Support .............................................................................................................................................................40 Rate Limiting Support .................................................................................................................................................41 Ingress Rate Limit...................................................................................................................................................41 Egress Rate Limit ...
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Register 17 (0x11): Reserved.................................................................................................................................60 Register 33 (0x21): Port 1 Control 1.......................................................................................................................60 Register 49 (0x31): Port 2 Control 1.......................................................................................................................60 Register 65 (0x41): Port 3 Control 1.......................................................................................................................60 Register 81 (0x51): Port 4 Control 1.......................................................................................................................60 Register 18 (0x12): Reserved.................................................................................................................................61 Register 34 (0x22): Port ...
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Register 61 (0x3D): Port 2 Control 6 ......................................................................................................................66 Register 77 (0x4D): Port 3 Control 6 for MAC Loop-back ......................................................................................66 Register 93 (0x5D): Port 4 Control 6 for MAC Loop-back ......................................................................................66 Register 30 (0x1E): Reserved ................................................................................................................................67 Register 46 (0x2E): Port 1 ...
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Register 146 (0x92): TOS Priority Control Register 2 ............................................................................................74 Register 147 (0x93): TOS Priority Control Register 3 ............................................................................................74 Register 148 (0x94): TOS Priority Control Register 4 ............................................................................................74 Register 149 (0x95): TOS Priority Control Register 5 ............................................................................................74 Register 150 (0x96): TOS ...
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Register 245 (0xF5): Port 4 Control 13...................................................................................................................78 Register 182 (0xB6): Reserved ..............................................................................................................................79 Register 198 (0xC6): Port 1 Rate Limit Control......................................................................................................79 Register 214 (0xD6): Port 2 Rate Limit Control......................................................................................................79 Register 230 (0xE6): Port 3 Rate Limit Control ......................................................................................................79 Register 246 (0xF6): ...
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Register 222 (0xDE): Port 2 Queue 3 Egress Limit Control 4 ................................................................................82 Register 238 (0xEE): Port 3 Queue 3 Egress Limit Control 4 ................................................................................82 Register 254 (0xFE): Port 4 Queue 3 Egress Limit Control 4 and Chip ID ............................................................82 Data ...
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List of Figures Figure 1. Typical Straight Cable Connection ............................................................................................................... 24 Figure 2. Typical Crossover Cable Connection ........................................................................................................... 25 Figure 3. Auto-Negotiation ........................................................................................................................................... 26 Figure 4. Destination Address Lookup Flow Chart, Stage 1 ........................................................................................ 30 Figure 5. Destination Address Resolution ...
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List of Tables Table 1. MDI/MDI-X Pin Definitions ............................................................................................................................. 23 Table 2. Internal Function Block Status ........................................................................................................................ 27 Table 3. Switch MAC 3 SW3-MII and MAC 4 SW4- MII Signals ................................................................................. 33 Table 4. MAC3 SW3-RMII and MAC4 SW4-RMII Connection..................................................................................... ...
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Pin Configuration September 2011 64-Pin QFN 13 M9999-092011-1.4 ...
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Pin Description Pin Number Pin Name 1 RXP1 2 RXM1 3 TXP1 4 TXM1 5 VDDA12 6 GND 7 ISET 8 VDDAT 9 RXP2 10 RXM2 11 TXP2 12 TXM2 13 VDDAT 14 INTR_N 15 VDDC 16 SM3TXEN 17 SM3TXD3 ...
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Pin Number Pin Name 26 SM3RXD2 27 SM3RXD1 28 SM3RXD0 29 SM3CRS 30 GND 31 SM3COL 32 SM4TXEN 33 SM4TXD3 34 SM4TXD2 35 SM4TXD1 36 SM4TXD0 37 SM4TXC/SM4REFCLK 38 VDDIO 39 SM4RXC 40 SM4RXDV/SM4CRSDV September 2011 (1) (2) Type Port ...
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Pin Number Pin Name 41 SM4RXD3 42 SM4RXD2 43 SM4RXD1 44 SM4RXD0 45 SM4COL 46 SM4CRS 47 SCONF1 48 SCONF0 49 P2LED1 September 2011 (1) (2) Type Port Pin Function MAC4 Switch MII receive bit 3. Strap option: IPD/O 4 ...
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Pin Number Pin Name 50 P2LED0 51 P1LED1 52 P1LED0 53 MDC 54 MDIO 55 SPIQ 56 SPIC/SCL 57 SPID/SDA 58 SPIS_N September 2011 (1) (2) Type Port Pin Function LED indicator for Port 2. Strap option: Switch MAC3 used ...
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Pin Number Pin Name 59 PS1 60 PS0 61 RST_N 62 VDDC Notes Power supply Input Output. I/O = Bidirectional. GND = Ground. IPU = Input w/internal pull-up. IPD ...
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Pin for Strap-in Options The KSZ8864RMN can function as a managed switch or unmanaged switch EEPROM or micro-controller exists, the KSZ8864RMN will operate from its default setting. The strap-in option pins can be configures by external pull-up/down resistors ...
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Pin Number Pin Name Type 48 SCONF0 IPD 49 P2LED1 IPU/O 50 P2LED0 IPU/O 51 P1LED1 IPU/O 52 P1LED0 IPU/O 59 PS1 IPD September 2011 (1) (2) Port Pin Function See pins configuration table below: Pin# (47,48) 00 (Default) 01 ...
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Notes Power supply Input Output. I/O = Bidirectional. GND = Ground. IPU = Input w/internal pull-up. IPD = Input w/internal pull-down. IPD/O = Input w/internal pull-down during reset, output pin otherwise. IPU/O = ...
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Introduction The KSZ8864RMN contains two 10/100 physical layer transceivers and four media access control (MAC) units with an integrated Layer 2 managed switch. The device runs in multiple modes. They are two copper + two MAC MII, two copper + ...
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Scrambler/De-Scrambler (100BASE-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register ...
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Straight Cable A straight cable connects an MDI device to an MDI-X device MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub ...
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Crossover Cable A crossover cable connects an MDI device to another MDI device MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). Auto-Negotiation The ...
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If auto-negotiation is not supported or the KSZ8864RMN link partner is forced to bypass auto-negotiation, then the KSZ8864RMN sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8864RMN to ...
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On-Chip Termination Resistors The KSZ8864RMN reduces board cost and simplifies board layout by using on-chip termination resistors for RX/TX differential pairs without the external termination resistors. The solution of the on chip termination and internal biasing will enhance much power ...
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Energy detect mode consists of two states, normal power state and low power state. While in low power state, the KSZ8864RMN reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The energy detect mode ...
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Aging The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process record is not updated for a period of time, the look-up ...
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On the transmit side, the KSZ8864RMN has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The ...
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Figure 5. Destination Address Resolution Flow Chart – Stage 2 September 2011 31 M9999-092011-1.4 ...
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The KSZ8864RMN will not forward the following packets: 1. Error Packets. These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors. 2. IEEE802.3x PAUSE Frames. KSZ8864RMN intercepts these packets and performs full duplex flow ...
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Switch MAC3/MAC4 SW3/SW4-MII Interface Table 3 shows two connection manners, 1. The first is an external MAC connects to SW3/SW4-MII PHY mode. 2. The second is an external PHY connects to SW3/SW4-MII MAC mode. Please see the pins [47, 48] ...
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The switch MII interface operates in either MAC mode or PHY mode for KSZ8864RMN. These interfaces are nibble- wide data interfaces and therefore run at one-quarter the network bit rate (not encoded). Additional signals on the transmit side indicate when ...
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SW3/4-RMII MAC to MAC Connection (“PHY” Mode) External KSZ8864RMN KSZ8864RMN SW MAC Signal REF_CLK SMxRXC SMxRXDV CRS_DV /SMxCRSDV RXD1 SMxRXD[1] RXD0 SMxRXD[0] TX_EN SMxTXEN TXD1 SMxTXD[1] TXD0 SMxTXD[0] (Not (Not Used) Used) (Clock comes from SMxTXC /SMxREFCLK Note: 1. ...
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The default of the device is clock mode because the P1LED1 is pulled up internally, the clock mode means the clock source comes from 25MHz crystal/oscillator on pins X1/X2, and the 50MHz clock will be output from the SMxRXC pin ...
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Ports 1 and 2, respectively. The KSZ8864RMN provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, ...
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Blocking state: only packets to the processor are forwarded. Learning is disabled. Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1" Software action: the processor should not send any packets to the port(s) in this ...
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Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.” Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be ...
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IGMP Support There are two parts involved to support the Internet Group Management Protocol (IGMP) in Layer 2. The first part is IGMP snooping, the second part is this IGMP packet to be sent back to the subscribed port. Describe ...
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DA Found in USE FID Static MAC Table Flag not Care No Do not Care Yes 0 Yes 1 Yes 1 Yes 1 SA+FID Found in Action Dynamic MAC Table No The SA+FID will be learned into the ...
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The two queues mode will use Q0Q1 for priority 01by bit [60] of the port register ingress limit control 12. The priority levels in the packets of ...
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Figure 8. KSZ8864RMN EEPROM Configuration Timing Diagram To configure the KSZ8864RMN with a pre-configured EEPROM use the following steps the board level, connect pin 56 on the KSZ8864RMN to the SCL pin on the EEPROM. Connect pin 57 ...
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To use the KSZ8864RMN SPI the board level, connect KSZ8864RMN pins as follows: KSZ8864RMN Pin KSZ8864RMN Signal Number Name 58 SPIS_N 56 SCL 57 SPID/SDA 55 SPIQ 2. Set the input signals PS[1:0] (pins 59 and 60, respectively) ...
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September 2011 Figure 11. SPI Multiple Write Figure 12. SPI Multiple Read 45 M9999-092011-1.4 ...
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MII Management Interface (MIIM) The KSZ8864RMN supports the standard IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8864RMN. An external device ...
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SMI register Read access is selected when OP Code is set to “10” and bits [2:1] of the PHY address is set to ‘11’. The 8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], ...
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Register Description Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers 2-13 0x02-0x0D Global Control Registers 14-15 0x0E-0x0F Power Down Management Control Registers 16-20 0x10-0x14 Reserved 21-23 0x15-0x17 Reserved (Factory Test Registers) 24-31 0x18-0x1F Reserved 32-36 0x20-0x24 Port 1 Control ...
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Offset Decimal Hex Description 192-206 0xC0-0xCE Port 1 Control Registers 207 0xCF Reserved (Factory Testing Register) 208-222 0xD0-0xDE Port 2 Control Registers 223 0xDF Reserved (Factory Testing Register) 224-238 0xE0-0xEE Port 3 Control Registers 239 0xEF Reserved (Factory Testing Register) ...
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Global Registers Address Name Register 0 (0x00): Chip ID0 7-0 family ID Register 1 (0x01): Revision ID / Start Switch 7-4 Reserved 3-1 Revision ID 0 Start Switch Register 2 (0x02): Global Control 0 7 New Back-off Enable 6 Reserved ...
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Address Name 4 Flush static MAC table 3 Reserved 2 Reserved 1 UNH Mode 0 Link Change Age Register 3 (0x03): Global Control 1 7 Pass All Frames 6 2K Byte packet support IEEE 802.3x Transmit 5 Flow Control Disable ...
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Address Name IEEE 802.3x Receive 4 Flow Control Disable 3 Frame Length Field Check 2 Aging Enable 1 fast age Enable Aggressive Back Off 0 Enable Register 4 (0x04): Global Control 2 Unicast Port-VLAN 7 Mismatch Discard Multicast Storm Protection ...
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Address Name Flow Control and Back 4 Pressure fair Mode No Excessive 3 Collision Drop 2 Huge Packet Support Legal Maximum Packet 1 Size Check Disable 0 Reserved Register 5 (0x05): Global Control 3 7 802.1q VLAN Enable IGMP Snoop ...
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Address Name Enable Pre-Tag on 4 Switch SW4-MII Interface 3-2 Reserved 1 Enable “Tag” Mask 0 Sniff Mode Select Register 6 (0x06): Global Control 4 Switch SW4-MII/RMII 7 Back Pressure Enable Switch SW4-MII/RMII 6 Half-Duplex Mode September 2011 Description 1, ...
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Address Name Switch SW4-MII/RMII 5 Flow Control Enable Switch SW4-MII/RMII 4 Speed 3 Null VID Replacement Broadcast Storm 2-0 Protection Rate Bit [10:8] Register 7 (0x07): Global Control 5 Broadcast Storm 7-0 Protection Rate Bit [7:0] Register 8 (0x08): Global ...
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Address Name Register 10 (0x0A): Global Control 8 7-0 Factory Testing Register 11 (0x0B): Global Control 9 Port 3 SW3-RMII reference clock edge 7 select Port 4 SW4- RMII 6 reference clock edge select 5 Reserved 4 Reserved PHY Power ...
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Address Name Register 12 (0x0C): Global Control 10 7 Reserved Satus of device with RMII interface at clock mode or normal mode, default is 6 clock mode with 25MHz Crystal clock from pins X1/ CPU interface clock ...
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Address Name 5 PLL Power Down Power Management Mode 2-0 Reserved Register 15 (0x0F): Power Down Management Control Go_sleep_time[7:0] September 2011 Description Pll power down enable Disable 0 = Enable PLL ...
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Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. Register 16 ...
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Address Name 0 Two Queues Split Enable Register 17 (0x11): Reserved Register 33 (0x21): Port 1 Control 1 Register 49 (0x31): Port 2 Control 1 Register 65 (0x41): Port 3 Control 1 Register 81 (0x51): Port 4 Control 1 Address ...
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Register 18 (0x12): Reserved Register 34 (0x22): Port 1 Control 2 Register 50 (0x32): Port 2 Control 2 Register 66 (0x42): Port 3 Control 2 Register 82 (0x52): Port 4 Control 2 Address Name 7 User Priority Ceiling 6 Ingress ...
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Register 19 (0x13): Reserved Register 35 (0x23): Port 1 Control 3 Register 51 (0x33): Port 2 Control 3 Register 67 (0x43): Port 3 Control 3 Register 83 (0x53): Port 4 Control 3 Address Name 7-0 Default Tag [15:8] Register 20 ...
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Register 87 (0x57): RMII Management Control Register Address Name Reserved Port 4 MAC4 SW4-RMII 3 50MHz clock output disable Reserved Register 25 (0x19): Reserved Register 41 (0x29): Port 1 Status 0 Register 57 (0x39): ...
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Register 26 (0x1A): Reserved Register 42 (0x2A): Port 1 PHY Special Control/Status Register 58 (0x3A): Port 2 PHY Special Control/Status Register 74 (0x4A): Reserved Register 90 (0x5A): Reserved Address Name 7-4 Reserved 3 Force_lnk 2 Pwrsave 1 Remote Loopback 0 ...
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Register 28 (0x1C): Reserved Register 44 (0x2C): Port 1 Control 5 Register 60 (0x3C): Port 2 Control 5 Register 76 (0x4C): Reserved Register 92 (0x5C): Reserved Address Name 7 Disable Auto-Negotiation 6 Forced Speed 5 Forced Duplex Advertised Flow Control ...
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Register 29 (0x1D): Reserved Register 45 (0x2D): Port 1 Control 6 Register 61 (0x3D): Port 2 Control 6 Register 77 (0x4D): Port 3 Control 6 for MAC Loop-back Register 93 (0x5D): Port 4 Control 6 for MAC Loop-back Address Name ...
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Register 30 (0x1E): Reserved Register 46 (0x2E): Port 1 Status 1 Register 62 (0x3E): Port 2 Status 1 Register 78 (0x4E): Reserved Register 94 (0x5E): Reserved Address Name 7 MDIX Status 6 AN Done 5 Link Good 4 Partner Flow ...
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Address Name 5 PHY Isolate 4 Soft Reset 3 Force Link 2-0 Port Operation Mode Indication Note: Port Control 12 and 13, 14 and Port Status 1,2 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register ...
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Advanced Control Registers Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in MAC pause control frames used for self MAC address filtering, see the register 134 also. ...
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Address Name Register 115 (0x73): Indirect Data Register 5 47-40 Indirect Data Register 116 (0x74): Indirect Data Register 4 39-32 Indirect Data Register 117 (0x75): Indirect Data Register 3 31-24 Indirect Data Register 118 (0x76): Indirect Data Register 2 23-16 ...
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The registers 128, 129 can be used to map from 802.1p priority field 0-7 to switch’s four priority queues 0-3, 0x3 is highest priority queues as priority 3, 0x0 is lowest priority queues as priority 0. Address Name Register 128 ...
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Address Name 4 Reserved Reserved 1 Reserved 0 Reserved Register 131 (0x83): Global Control 15 7 Reserved 6 Reserved 5 Unknown unicast packet forward Unknown unicast packet forward port map Register 132 (0x84): Global ...
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Address Name Register 134 (0x86): Global Control 18 7 Reserved 6 Self Address Filter Enable 5 Unknown IP multicast packet forward Unknown IP multicast packet forward port map Register 135 (0x87): Global Control 19 7 Reserved 6 ...
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Address Name DSCP[5: DSCP[3: DSCP[1:0] Register 145 (0x91): TOS Priority Control Register DSCP[15:14 DSCP[13:12 DSCP[11:10 DSCP[9:8] Register 146 ...
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Address Name Register 150 (0x96): TOS Priority Control Register DSCP[55:54 DSCP[53:52 DSCP[51:50 DSCP[49:48] Register 151 (0x97): TOS Priority Control Register DSCP[63:62 ...
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Address Name Register 157 (0x9D): TOS Priority Control Register DSCP[111:110 DSCP[109:108 DSCP[107:106 DSCP[105:104] Register 158 (0x9E): TOS Priority Control Register DSCP[119:118 ...
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Address Name 1 Insert Source Port PVID for Untagged Packet Destination to Second Lowest Egress Port Note: Enabled by the register 135 bit 2 0 Reserved Register 177 (0xB1): Reserved Register 193 (0xC1): Port 1 Control 9 Register 209 (0xD1): ...
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Address Name Register 179 (0xB3): Reserved Register 195 (0xC3): Port 1 Control 11 Register 211 (0xD3): Port 2 Control 11 Register 227 (0xE3): Port 3 Control 11 Register 243 (0xF3): Port 4 Control 11 7 Enable Port Transmit Queue 2 ...
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Address Name Register 182 (0xB6): Reserved Register 198 (0xC6): Port 1 Rate Limit Control Register 214 (0xD6): Port 2 Rate Limit Control Register 230 (0xE6): Port 3 Rate Limit Control Register 246 (0xF6): Port 4 Rate Limit Control 7 - ...
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Address Name Register 184 (0xB8): Reserved Register 200 (0xC8): Port 1 Priority 1 Ingress Limit Control 2 Register 216 (0xD8): Port 2 Priority 1 Ingress Limit Control 2 Register 232 (0xE8): Port 3 Priority 1 Ingress Limit Control 2 Register ...
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Address Name Register 187 (0xBB): Reserved Register 203 (0xCB): Port 1 Queue 0 Egress Limit Control 1 Register 219 (0xDB): Port 2 Queue 0 Egress Limit Control 1 Register 235 (0xEB): Port 3 Queue 0 Egress Limit Control 1 Register ...
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Address Name Register 190 (0xBE): Reserved Register 206 (0xCE): Port 1 Queue 3 Egress Limit Control 4 Register 222 (0xDE): Port 2 Queue 3 Egress Limit Control 4 Register 238 (0xEE): Port 3 Queue 3 Egress Limit Control 4 Register ...
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Data Rate Selection Table in 10BT Rate for 10BT mode 1 Mbps <= rate <= 9 Mbps rate = 10 Mbps Less than 1Mbps see as below 64 Kbps 128 Kbps 192 Kbps 256 Kbps 320 Kbps 384 Kbps 448 ...
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Address Name Register 223(0xDF): Port3 Control Register 2 7 Reserved Select Switch Port 3 MAC 3 6 SW3-MII interface mode Reserved Register 239(0xEF): Test Register 3 7-0 Reserved Register 255(0xFF): Testing and Port 4 Control Register 7 ...
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Static MAC Address Table KSZ8864RMN has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table ...
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Address Name 52-48 Forwarding Ports 47-0 MAC Address (DA) September 2011 Description The 5 bits control the forward ports, example: 00001, Reserved 00010, forward to port 1 ….. 10000, forward to port 4 00110, forward to port 1 and port ...
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Examples: (1) Static Address Table Read (read the 2nd entry) Write to Register 110 with 0x10 (read static table selected) Write to Register 111 with 0x1 (trigger the read operation) Then Read Register 113 (63-56) Read Register 114 (55-48) Read ...
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VLAN Table The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit 7 = 1), this table is used to retrieve VLAN information that is associated with the ingress packet. The fields ...
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Examples: (1) VLAN Table Read (read the VID=2 entry) Write the indirect control and address registers first Write to Register 110 (0x6E) with 0x14 (read VLAN table selected) Write to Register 111 (0x6F) with 0x0 (trigger the read operation for ...
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Dynamic MAC Address Table This table is read only. The contents are maintained by the KSZ8864RMN only. Address Name Format of Dynamic MAC Address Table (1K entries) 71 MAC Empty 70- Valid Entries 60-59 Time Stamp 58-56 Source ...
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Dynamic MAC Address Table Read (read the 257 Write to Register 110 with 0x19 (read dynamic table selected) Write to Register 111 with 0x1 (trigger the read operation) and then Read Register 112 (71-64) Read Register 113 (63-56) Read ...
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MIB (Management Information Base) Counters The MIB counters are provided on per port basis. These counters are read using indirect memory access as below: For Port 1 Offset Counter Name 0x20 RxLoPriorityByte 0x21 RxHiPriorityByte 0x22 RxUndersizePkt 0x23 RxFragments 0x24 RxOversize ...
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For Port 2, the base is 0x40, same offset definition (0x40-0x5f) For Port 3, the base is 0x60, same offset definition (0x60-0x7f) For Port 4, the base is 0x80, same offset definition (0x80-0x9f) Address Name Format of Per Port MIB ...
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Programming Examples: (1) MIB counter read (read port 1 Rx64Octets counter) Write to Register 110 with 0x1c (read MIB counters selected) Write to Register 111 with 0x2e (trigger the read operation) Then Read Register 117 (counter value 31-24 ...
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MIIM Registers All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms used for MIIM and SPI. The “PHYAD” defined in KSZ8864RMN is assigned as “0x2” for port 1, “0x3” for ...
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Address Name 2 Disable far End fault 1 Disable Transmit 0 Disable LED Register 1h: MII Status 15 T4 Capable 14 100 Full Capable 13 100 Half Capable 12 10 Full Capable 11 10 Half Capable 10-7 Reserved 6 Preamble ...
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Address Name 12-11 Reserved 10 Pause 9 Reserved 8 Adv 100 Full 7 Adv 100 Half 6 Adv 10 Full 5 Adv 10 Half 4-0 Selector Field Register 5h: Link Partner Ability 15 Next Page 14 LP ACK 13 Remote ...
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Address Name Register 1fh: PHY Special Control/Status 15-11 Reserved 10-8 Port Operation Mode Indication 7-6 Reserved 5 Polrvs 4 MDI-X status 3 Force_lnk 2 Pwrsave 1 Remote Loopback 0 Reserved September 2011 Description Indicate the current state of port operation ...
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Absolute Maximum Ratings Supply Voltage ( ..................................–0.5V to +2.4V DDAR DDC ( .................................–0.5V to +4.0V DDAT DDIO Input Voltage ........................................–0.5V to +4.0V Output Voltage .....................................–0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..............260°C Storage ...
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Symbol Parameter TTL Inputs V Input High Voltage (VDDIO=3.3/2.5/1.8V Input Low Voltage (VDDIO=3.3/2.5/1.8V Input Current (Excluding Pull-up/Pull-down) IN TTL Outputs V Output High Voltage (VDDIO=3.3/2.5/1.8V Output Low Voltage (VDDIO=3.3/2.5/1.8V Output Tri-State Leakage ...
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Timing Diagrams EEPROM Timing Figure 13. EEPROM Interface Input Receive Timing Diagram Figure 14. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter t Clock Cycle CYC1 t Set-Up Time S1 t Hold Time H1 t Output Valid OV1 September 2011 ...
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MII Timing Figure 15. MAC Mode MII Timing – Data Received from MII Figure 16. MAC Mode MII Timing – Data Transmitted from MII Symbol t CYC3 OV3 September 2011 10Base-T/100Base-TX Parameter Min. Typ. Clock ...
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Figure 18. PHY Mode MII Timing – Data Transmitted from MII September 2011 Figure 17. PHY Mode MII Timing – Data Received from MII Symbol Parameter Min t Clock Cycle CYC4 t Set-Up Time Hold Time 0 ...
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RMII Timing Receive Tim ing REFCLK CRSDV RXD[1:0] Timing Parameter t cyc t ...
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SPI Timing SPIS_N tCHSL SPIC tDVCH SPID SPIQ Symbol Parameter f Clock Frequency C t SPIS_N Inactive Hold Time CHSL t SPIS_N Active Set-Up Time SLCH t SPIS_N Active Hold Time CHSH t SPIS_N Inactive Set-Up Time SHCH t SPIS_N ...
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Symbol Parameter f Clock Frequency C t SPIQ Hold Time CLQX t Clock Low to SPIQ Valid CLQV t Clock High Time CH t Clock Low Time CL t SPIQ Rise Time QLQH t SPIQ fall Time QHQL t SPIQ ...
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Auto-Negotiation Timing Symbol Parameter t FLP burst to FLP burst BTB t FLP burst width FLPW t Clock/Data pulse width PW t Clock pulse to Data pulse CTD t Clock pulse to Clock pulse CTC Number of Clock/Data pulse per ...
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MDC/MDIO Timing Timing Parameter Description t MDC period P t MDIO (PHY input) setup to rising edge of MDC 1MD1 t MDIO (PHY input) hold from rising edge of MDC MD2 t MDIO (PHY output) delay from rising edge of ...
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Reset Timing Symbol Parameter t Stable Supply Voltages to Reset High SR t Configuration Set-Up Time CS t Configuration Hold Time CH t Reset to Strap-In Pin Output RC tvr 3.3V rise time September 2011 Figure 25. Reset Timing Table ...
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Reset Circuit Diagram Micrel recommends the following discrete reset circuit, as shown in Figure 26, when powering up the KS8895MQ device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), Micrel recommends the ...
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Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common- mode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps of RX/TX ...
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Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this ...