KSZ8864RMNI MICREL [Micrel Semiconductor], KSZ8864RMNI Datasheet - Page 22

• Manufacturer Part Number: KSZ8864RMNI
• Description: Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
KSZ8864RMN
Introduction
The KSZ8864RMN contains two 10/100 physical layer transceivers and four media access control (MAC) units with
an integrated Layer 2 managed switch. The device runs in multiple modes. They are two copper + two MAC MII, two
copper + two MAC RMII, two copper + 1 MAC MII+ 1 MAC RMII and two copper + 1 MAC MII or 1 MAC RMII. Those
are useful for implementing multiple products in many applications.
The KSZ8864RMN has the flexibility to reside in a managed or unmanaged design. In a managed design, a host
processor has complete control of the KSZ8864RMN via the SPI bus, or partial control via the MDC/MDIO interface.
An unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time.
On the media side, the KSZ8864RMN supports IEEE 802.3 10BASE-T, 100BASE-TX on all ports with Auto
MDI/MDIX. The KSZ8864RMN can be used as fully managed 4-port switch through two microprocessors by its two
MII interface or RMII interface for an advance management application.
Physical signal transmission and reception are enhanced through the use of patented analog circuitry with enhanced
mix signal technology that makes the design more efficient and allows for lower power consumption and smaller chip
die size.
The major enhancements of the KSZ8864RMN is small package with configuble of two MII and RMII modes for two
MAC interfaces. The KSZ8864RMN supports more new features for host processor management, multiple kind of
packets filtering, tag as well as port based VLAN, rapid spanning tree support, IGMP snooping support, port mirroring
support and more flexible rate limiting and more functionality.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts
the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B
coding followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then
transmitted in MLT3 current output. The output current is set by an external 1% 12.4kΩ resistor for the 1:1
transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding
amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the
100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data
and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The
receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to
adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial
estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes
itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as
temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is
used to compensate for the effect of baseline wander and improve the dynamic range. The differential data
conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by
the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the
MAC.
PLL Clock Synthesizer
The KSZ8864RMN generates 125MHz, 83MHz, 41MHz, 25MHz and 10MHz clocks for system timing. Internal clocks
are generated from an external 25MHz crystal or oscillator.
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September 2011
M9999-092011-1.4