KSZ8864RMNI MICREL [Micrel Semiconductor], KSZ8864RMNI Datasheet - Page 12

• Manufacturer Part Number: KSZ8864RMNI
• Description: Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
KSZ8864RMN
List of Tables
Table 1. MDI/MDI-X Pin Definitions ............................................................................................................................. 23
Table 2. Internal Function Block Status ........................................................................................................................ 27
Table 3. Switch MAC 3 SW3-MII and MAC 4 SW4- MII Signals ................................................................................. 33
Table 4. MAC3 SW3-RMII and MAC4 SW4-RMII Connection..................................................................................... 35
Table 5. Tail Tag Rules ................................................................................................................................................. 39
Table 6. FID+DA Look-Up in the VLAN Mode ............................................................................................................. 41
Table 7. FID+SA Look-Up in the VLAN Mode.............................................................................................................. 41
Table 8. SPI Connections ............................................................................................................................................ 44
Table 9. MII Management Interface Frame Format ..................................................................................................... 46
Table 10. Serial Management Interface (SMI) Frame Format ..................................................................................... 46
Table 11. 100BT Rate Selection for the Rate limit....................................................................................................... 82
Table 12. 10BT Rate Selection for the Rate Limit........................................................................................................ 83
Table 13. Static MAC Address Table ........................................................................................................................... 86
Table 14. VLAN Table .................................................................................................................................................. 88
Table 15. VLAN ID and Indirect Registers ................................................................................................................... 89
Table 16. Dynamic MAC Address Table ...................................................................................................................... 90
Table 17. Port-1 MIB Counter Indirect Memory Offsets............................................................................................... 92
Table 18. Format of “Per Port” MIB Counter................................................................................................................ 93
Table 19. All Port Dropped Packet MIB Counters........................................................................................................ 93
Table 20. Format of “All Dropped Packet” MIB Counter .............................................................................................. 93
Table 21. EEPROM Timing Parameters .................................................................................................................... 101
Table 22. MAC Mode MII Timing Parameters............................................................................................................ 102
Table 23. PHY Mode MII Timing Parameters ............................................................................................................ 103
Table 24. RMII Timing Parameters ............................................................................................................................ 104
Table 25. SPI Input Timing Parameters ..................................................................................................................... 105
Table 26. SPI Output Timing Parameters .................................................................................................................. 106
Table 27. Auto-Negotiation Timing Parameters......................................................................................................... 107
Table 28. MDC/MDIO Typical Timing Parameters..................................................................................................... 108
Table 29. Reset Timing Parameters .......................................................................................................................... 109
Table 30. Transformer Selection Criteria ................................................................................................................... 111
Table 31. Qualified Magnetic Vendors ....................................................................................................................... 111
Table 32. Typical Reference Crystal Characteristics ................................................................................................. 111
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September 2011
M9999-092011-1.4