KSZ8864RMNI MICREL [Micrel Semiconductor], KSZ8864RMNI Datasheet - Page 67

• Manufacturer Part Number: KSZ8864RMNI
• Description: Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces
• Manufacturer: MICREL [Micrel Semiconductor]

September 2011
Register 30 (0x1E): Reserved
Register 46 (0x2E): Port 1 Status 1
Register 62 (0x3E): Port 2 Status 1
Register 78 (0x4E): Reserved
Register 94 (0x5E): Reserved
Register 31 (0x1F): Reserved
Register 47 (0x2F): Port 1 Control 7 and Status 2
Register 63 (0x3F): Port 2 Control 7 and Status 2
Register 79 (0x4F): Reserved
Register 95 (0x5F): Reserved
Address
7
6
5
4
3
2
1
0
Address
7
6
Name
MDIX Status
AN Done
Link Good
Partner Flow Control
Capability
Partner 100BT Full-
Duplex Capability
Partner 100BT Half-
Duplex Capability
Partner 10BT Full-Duplex
Capability
Partner 10BT Half-Duplex
Capability
Name
PHY Loopback
Reserved
Description
1, MDI-X.
0, MDI.
1, AN done.
0, AN not done.
1, link good.
0, link not good.
1, link partner flow control capable.
0, link partner not flow control capable.
1, link partner 100BT full-duplex capable.
0, link partner not 100BT full-duplex capable.
1, link partner 100BT half-duplex capable.
0, link partner not 100BT half-duplex capable.
1, link partner 10BT full-duplex capable.
0, link partner not 10BT full-duplex capable.
1, link partner 10BT half-duplex capable.
0, link partner not 10BT half-duplex capable.
Description
1 = Perform PHY loopback, loop back path as follows:
E.g. set port 1 PHY Loopback (reg. 47, bit 7 = ‘1’)
Use the port 2 as monitor port. The packets will
transfer
loopback on port 2 with monitor port 1.
0 = Normal Operation.
N/A Do not change
Start: Port 2 receiving (also can start from port 1).
Loopback: PMD/PMA of port 1’s PHY
End: Port 2 transmitting (also can end at port 1).
Setting reg. 63 bit 7 = ‘1’ will perform PHY
67
Mode
Mode
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
M9999-092011-1.4
Default
Default
0
0
0
0
0
0
0
0
0
0