PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 130

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J11 FAMILY
9.6
External interrupts on the INT0, INT1, INT2 and INT3
pins are edge-triggered. If the corresponding INTEDGx
bit in the INTCON2 register is set (= 1), the interrupt is
triggered by a rising edge; if the bit is clear, the trigger
is on the falling edge. When a valid edge appears on
the INTx pin, the corresponding flag bit and INTxIF are
set. This interrupt can be disabled by clearing the
corresponding enable bit, INTxIE. Flag bit, INTxIF,
must be cleared in software in the Interrupt Service
Routine before re-enabling the interrupt.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the Sleep and Idle modes
if bit, INTxIE, was set prior to going into the power-man-
aged modes. After waking from Sleep or Idle mode, the
processor will branch to the interrupt vector if the
Global Interrupt Enable bit (GIE) is set. Deep Sleep
mode can wake up from INT0, but the processor will
start execution from the Power-on Reset vector rather
than branch to the interrupt vector.
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the Interrupt Priority bits,
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and
INT3IP (INTCON2<1>). There is no priority bit
associated with INT0. It is always a high-priority
interrupt source.
9.7
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh  00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
EXAMPLE 9-1:
DS39932D-page 130
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INTx Pin Interrupts
TMR0 Interrupt
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in access bank
; STATUS_TEMP located anywhere
; BSR_TEMP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
module.
pair (FFFFh  0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt prior-
ity bit, TMR0IP (INTCON2<2>). See
“Timer0 Module”
9.8
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.9
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see
“Data Memory
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved.
STATUS and BSR registers during an Interrupt Service
Routine.
Example 9-1
PORTB Interrupt-on-Change
Context Saving During Interrupts
Organization”), the user may need to
for further details on the Timer0
saves and restores the WREG,
 2011 Microchip Technology Inc.
Section 12.0
Section 6.3