PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 312

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J11 FAMILY
A typical transmit sequence would go as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The MSSP module generates an interrupt at the
11. The user generates a Stop condition by setting
12. Interrupt is generated once the Stop condition is
DS39932D-page 312
The user generates a Start condition by setting
the Start Enable bit, SEN (SSPxCON2<0>).
SSPxIF is set. The MSSP module will wait for
the required start time before any other
operation takes place.
The user loads the SSPxBUF with the slave
address to transmit.
Address is shifted out of the SDAx pin until all
8 bits are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
The user loads the SSPxBUF with 8 bits of data.
Data is shifted out the SDAx pin until all 8 bits
are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
end of the ninth clock cycle by setting the
SSPxIF bit.
the Stop Enable bit, PEN (SSPxCON2<2>).
complete.
19.5.7
In I
the lower seven bits of the SSPxADD register
(Figure
Baud Rate Generator will automatically begin counting.
The BRG counts down to 0 and stops until another
reload has taken place. The BRG count is decre-
mented twice per instruction cycle (T
Q4 clocks. In I
automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 19-3
instruction cycles and the BRG value loaded into
SSPxADD. The SSPADD BRG value of 0x00 is not
supported.
2
C Master mode, the BRG reload value is placed in
19-19). When a write occurs to SSPxBUF, the
BAUD RATE
demonstrates clock rates based on
2
C Master mode, the BRG is reloaded
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CY
) on the Q2 and