LAN91C100-FD SMSC [SMSC Corporation], LAN91C100-FD Datasheet - Page 35

• Manufacturer Part Number: LAN91C100-FD
• Description: FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
• Manufacturer: SMSC [SMSC Corporation]

Note:
SMSC DS – LAN91C100FD Rev. D
FEAST Fast Ethernet Controller with Full Duplex Capability
RX_DISC
RX_DISC
INT
INT
0
OFFSET
OFFSET
This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A
MASK bit being set will cause a hardware interrupt.
The Bit 7 mask must never be written high (1).
RX_DISC INT - Set when the nRXDISC PIN COUNTER in the ERCV register increments to a value of FF.
The RX_DISC INT bit latches the condition for the purpose of being polled or generating an interrupt, and
will only be cleared by writing the acknowledge register with the RX_DISC INT bit set.
ERCV INT - Early receive interrupt. Set whenever a receive packet is being received, and the number of
bytes received into memory exceeds the value programmed as ERCV THRESHOLD (Bank 3, Offset Ch).
ERCV INT stays set until acknowledged by writing the INTERRUPT ACKNOWLEDGE REGISTER with the
ERCV INT bit set.
EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special
conditions. This bit merges exception type of interrupt sources, whose service time is not critical to the
execution speed of the low level drivers. The exact nature of the interrupt can be obtained from the EPH
Status Register (EPHSR), and enabling of these sources can be done via the Control Register. The
possible sources are:
1.
2.
3.
Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register.
1) LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit Error
Enable)
EPH INT will only be cleared by the following methods:
C
D
LINK - Link Test transition
CTR_ROL - Statistics counter roll over
TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low
and the specific reason will be reflected by the bits:
3.1
3.2
3.3
3.4
3.5
ERCV INT
ERCV INT
TXUNRN - Transmit under-run
SQET - SQE Error
LOST CARR - Lost Carrier
LATCOL - Late Collision
16COL - 16 collisions
0
INTERRUPT ACKNOWLEDGE
INTERRUPT MASK REGISTER
EPH INT
0
REGISTER
NAME
NAME
PRELIMINARY
RX_OVRN
RX_OVRN
INT
INT
0
Page 35
ALLOC
INT
0
READ/WRITE
WRITE ONLY
TYPE
TYPE
TX EMPTY
TX EMPTY
INT
INT
0
TX INT
TX INT
0
SYMBOL
SYMBOL
ACK
MSK
Rev. 10/14/2002
RCV INT
0