LAN9218-MT-E2 SMSC [SMSC Corporation], LAN9218-MT-E2 Datasheet - Page 104
![no-image](/images/no-image-200.jpg)
LAN9218-MT-E2
Manufacturer Part Number
LAN9218-MT-E2
Description
High-Performance Single- Chip 10/100 Ethernet Controller with HP Auto-MDIX
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LAN9218-MT-E2.pdf
(130 pages)
- Current page: 104 of 130
- Download datasheet (2Mb)
Revision 1.5 (07-18-06)
5.5.1
BITS
6-0
15
14
13
12
11
10
9
8
7
Reset. 1 = software reset. Bit is self-clearing. For best results, when setting
this bit do not set other bits in this register.
Loopback. 1 = loopback mode, 0 = normal operation
Speed Select. 1 = 100Mbps, 0 = 10Mbps. Ignored if Auto Negotiation is
enabled (0.12 = 1).
Auto-Negotiation Enable. 1 = enable auto-negotiate process (overrides
0.13 and 0.8) 0 = disable auto-negotiate process.
Power Down. 1 = General power down-mode, 0 = normal operation.
Note:
Reserved
Restart Auto-Negotiate. 1 = restart auto-negotiate process 0 = normal
operation. Bit is self-clearing.
Duplex Mode. 1 = full duplex, 0 = half duplex. Ignored if Auto Negotiation
is enabled (0.12 = 1).
Collision Test. 1 = enable COL test, 0 = disable COL test
Reserved
Basic Control Register
Note 5.1
Index (In Decimal):
After this bit is cleared, the PHY may auto-negotiate with it's
partner station. This process may take a few seconds to complete.
Once auto-negotiation is complete, bit 5 of the PHY's Basic Status
Register will be set.
This default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the
pin description section for more details
DESCRIPTION
0
DATASHEET
104
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Size:
16-bits
RW/SC
RW/SC
TYPE
RW
RW
RW
RW
RW
RW
RO
RO
See
See
SMSC LAN9218
DEFAULT
Note 5.1
Note 5.1
Datasheet
0
0
0
0
0
0
0
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