PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 324

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F66K80 FAMILY
21.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
FIGURE 21-19:
TABLE 21-3:
DS39977C-page 324
Note 1:
2
C Master mode, the Baud Rate Generator (BRG)
16 MHz
2:
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
F
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
A minimum 16-MHz F
BAUD RATE
(2)
2
C interface does not conform to the 400 kHz I
(Figure
I
2
C™ CLOCK RATE w/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C Master mode, the BRG is
21-19). When a write occurs
SSPM<3:0>
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
4 MHz
SCL
F
OSC
CY
is required for 1 MHz I
SSPM<3:0>
CY
) on the
Control
Reload
Preliminary
CLKO
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
CY
* 2
Reload
2
C.
2
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 21-3
instruction cycles and the BRG value loaded into
SSPADD. The SSPADD BRG value of 00h is not
supported.
BRG Down Counter
C specification (which applies to rates greater than
SSPADD<6:0>
demonstrates clock rates based on
BRG Value
0Ch
18h
1Fh
63h
09h
27h
02h
09h
03h
 2011 Microchip Technology Inc.
F
OSC
/4
(2 Rollovers of BRG)
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
100 kHz
308 kHz
100 kHz
100 kHz
F
SCL
(1)
(1)
(1)
(1)