PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 80

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F66K80 FAMILY
TABLE 4-4:
DS39977C-page 80
PRI_IDLE mode
SEC_IDLE mode
RC_IDLE mode
Sleep mode
Note 1:
Power-Managed
2:
3:
4:
5:
T
runs concurrently with any other required delays (see
Includes postscaler derived frequencies. On Reset, INTOSC defaults to HF-INTOSC at 8 MHz.
T
(Parameter F12,
Execution continues during T
The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>)
and FOSC (CONFIG1H<3:0>) bits.
Mode
CSD
OST
(Parameter 38,
is the Oscillator Start-up Timer (Parameter 32,
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Table
Table
31-7); it is also designated as T
Clock Source
31-11) is a required delay when waking from Sleep and all Idle modes, and
MF-INTOSC
MF-INTOSC
MF-INTOSC
HF-INTOSC
HF-INTOSC
HF-INTOSC
IOBST
LF-INTOSC
LF-INTOSC
LF-INTOSC
LP, XT, HS
LP, XT, HS
EC, RC
EC, RC
HSPLL
HSPLL
SOSC
(Parameter 39,
Preliminary
(2)
(2)
(2)
(2)
(2)
(2)
(5)
Table
Table
Section 4.4 “Idle Modes”
PLL
31-11), the INTOSC stabilization period.
.
31-11). T
T
Exit Delay
OST
T
T
T
T
T
T
IOBST
CSD
CSD
CSD
CSD
OST
+ t
RC
(1)
(1)
(1)
(3)
(1)
rc
(4)
(3)
is the PLL Lock-out Timer
 2011 Microchip Technology Inc.
).
Clock Ready
Status Bits
SOSCRUN
MFIOFS
MFIOFS
MFIOFS
HFIOFS
HFIOFS
HFIOFS
OSTS
OSTS
None
None
None