PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 337

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 21-4:
 2011 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
TRISC
SSPBUF
SSPADD
SSPMSK
SSPCON1
SSPCON2
SSPSTAT
PMD0
ODCON
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used by the MSSP module in I
Note 1:
Name
2:
(1)
SSPMSK shares the same address in SFR space as SSPADD, but is only accessible in certain I
Slave operating modes in 7-Bit Masking mode. See
more details.
Alternate bit definitions for use in I
MSSP Address Register (I
MSSP Baud Rate Reload Register (I
MSSP Receive Buffer/Transmit Register
GIE/GIEH PEIE/GIEL
CCP5MD
OSCFIF
OSCFIE
OSCFIP
TRISC7
SSPOD
REGISTERS ASSOCIATED WITH I
WCOL
PSPIF
PSPIE
PSPIP
GCEN
GCEN
MSK7
Bit 7
SMP
ACKSTAT
ACKSTAT
CCP4MD
CCP5OD
TRISC6
SSPOV
MSK6
ADIF
ADIE
ADIP
Bit 6
CKE
—
—
—
ADMSK5
2
CCP3MD
CCP4OD
TMR0IE
C™ Slave mode),
TRISC5
SSPEN
ACKDT
RC1IF
RC1IE
RC1IP
MSK5
Bit 5
D/A
2
—
—
—
C Slave mode operations only.
(2)
Preliminary
2
C Master mode)
ADMSK4
CCP2MD
CCP3OD
TRISC4
ACKEN
INT0IE
TX1IF
TX1IE
TX1IP
MSK4
Bit 4
CKP
2
—
—
—
C™ OPERATION
P
PIC18F66K80 FAMILY
Section 21.4.3.4 “7-Bit Address Masking Mode”
(2)
ADMSK3
CCP1MD
CCP2OD
TRISC3
SSPM3
SSPIE
SSPIP
SSPIF
BCLIF
BCLIE
BCLIP
RCEN
MSK3
RBIE
Bit 3
S
(2)
ADMSK2
UART2MD UART1MD
TMR1GIE
TMR1GIP
TMR1GIF
CCP1OD
TMR0IF
HLVDIF
HLVDIE
HLVDIP
TRISC2
SSPM2
MSK2
Bit 2
PEN
R/W
(2)
ADMSK1
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISC1
SSPM1
INT0IF
2
MSK1
RSEN
U2OD
Bit 1
C™ mode.
UA
DS39977C-page 337
(2)
TMR3GIF
TMR3GIE
TMR3GIP
2
TMR1IF
TMR1IE
TMR1IP
TRISC0
SSPMD
SSPM0
C™
U1OD
MSK0
RBIF
Bit 0
SEN
SEN
BF
for