TMC2250AG1C2 FAIRCHILD [Fairchild Semiconductor], TMC2250AG1C2 Datasheet - Page 12
![no-image](/images/no-image-200.jpg)
TMC2250AG1C2
Manufacturer Part Number
TMC2250AG1C2
Description
Matrix Multiplier 12 x 10 bit, 50 MHz
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
1.TMC2250AG1C2.pdf
(23 pages)
PRODUCT SPECIFICATION
3 x 3 Pixel Convolver (Mode 10)
This filter configuration accepts a 3 pixel-square neighbor-
hood, side-loaded three pixels at a time through input ports
A, B and C, and multiplies the 9 most recent pixel values by
the coefficient set currently stored in the registers. These
products are summed with the data presented to the cascade
input, and a new 3-cycle impulse response, rounded to 16
bits, is available at the output port 5 to 7 clocks later, with a
new output available on every clock cycle.
The input pixel data are automatically shifted one location to
the right through the three rows of multiplier input registers
on every clock in anticipation of three new input data words,
effectively sliding the convolutional window over one col-
umn in an image plane.
12
CLK
CWE
KA, KB, KC
DATA IN A, B, C
MODE 10
CASIN
CASOUT
01
K_1
1
Figure 5. 3 x 3-Pixel Convolver Impulse Response (Mode 10)
K_2
10
2
K_3
1.0
11
3
4
5
A(3)KA3(3)+A(2)KA2(2)+A(1)KA1(1)
+B(3)KB3(3)+B(2)KB2(2)+B(1)KB1(1)
+C(3)KC3(3)+C(2)KC2(2)+C(1)KC1(1)
Latency: Impulse in to center of 3-tap response = 6 registers.
Cascade In to Cascade Out=4 registers.
6
Q 17
01
7
CASOUT(7)=
K j = KA j + KB j + KC j
K 3
8
K 2
+CASIN(4)
9
K 1
10
REV. 1.0.2 10/25/00
Q 7
11
TMC2250A