TMC2250AG1C2 FAIRCHILD [Fairchild Semiconductor], TMC2250AG1C2 Datasheet - Page 7
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TMC2250AG1C2
Manufacturer Part Number
TMC2250AG1C2
Description
Matrix Multiplier 12 x 10 bit, 50 MHz
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
1.TMC2250AG1C2.pdf
(23 pages)
TMC2250A
Pin Descriptions
Notes:
1. The output ports X, Y, Z and CASOUT, and input port CASIN are internally reconfigured by the device as required for each
2. The output drivers on pins XC
Table 3. Configuration Mode Word
REV. 1.0.2 10/25/00
Pin Name
KA
KB
KC
XC
YC
Y
YC
ZC
MODE
7-4
mode of the device. The multiple-function pins have names which are combinations of these titles, as appropriate.
power-up. If these pins are to be tied to other output drivers, to each other, or to ground or V
a clock pulse arrives within a few seconds of power-up, to avoid bus contention.
9-0
9-0
11-0
9-0
11-0
11-8
3-0
00
01
10
11
1,0
N5, M5, N4, L5
B4, A3, A2, B3,
A1, C3, B2, B1,
D3, C2, C1, D2
F1, G2, G1, H1 14, 15, 17, 18 Output
K13, J11, K12,
D1, E2, E1, F2 9, 10, 11, 13
L13, L12, K11,
CPGA/PPGA/
M10, L9, N10,
K1, J2, J1, H2 23, 22, 21, 19 CASOUT
M7, N6, M6,
M4, N3, M3,
M8, N8, N7,
N2, M2, L3,
N1, L2, K3,
M9, N9, L8
M1, L1, K2
M13, M12,
M11, L10,
N12, N11,
L11, N13
3 x 3 Matrix Multiply
9-Tap One Dimensional FIR
3 x 3 -Pixel Convolver
4 x 2 -Pixel Convolver
MPGA
Pin Number
Configuration Mode
(continued)
69, 68, 67, 66,
65, 64, 63, 62,
59, 58, 57, 56,
55, 54, 53, 52,
49, 48, 47, 45,
44, 43, 41, 40,
120, 1, 2, 3, 4,
37, 36, 35, 33,
32, 31, 30, 29,
28, 27, 26, 25
115, 116,
117, 119,
11-0
MQFP
61, 60
51, 50
39, 38
5, 6, 7
and YC
11-8
Function
Coefficient
Input A1, A2,
A3
Coefficient
Input B1, B2,
B3
Coefficient
Input B1, B2,
B3
CASIN
Output X
CASIN
Output Y
Output Y
CASOUT
Output Z
are not necessarily disabled until after the first rising edge of CLK following
7-4
15-4
3-0
11-0
11-0
3-0
3-0
15-4
/
only
/
/
/
Table 4. Coefficient Write Enable Word
Pin Description
Data presented to the 10-bit registered coefficient
input ports KA, KB and KC are latched three at a time
into the internal coefficient storage register set
indicated by the Coefficient Write Enable CWE
the next clock, as shown in Table 4.
In all modes except Mode 00, the x port and four bits
of the Y output port are reconfigured as the 16-bit
registered Cascade Input port CASIN
presented to this input will be added to the weighted
sums of the data words which were presented to the
input ports (A, B and C).
In the matrix multiply mode, data are available at the
12-bit registered output ports X, Y AND Z t
every clock. These ports are reconfigured in the
filtering modes as 16-bit Cascade Input and Output
ports.CASOUT
In all modes except Mode 00, the Z port and four bits
of the Y output port are reconfigured as the 16-bit
registered Cascade Output port CASOUT
CWE
00
01
10
11
1,0
Hold all registers
Update KA1, KB1, KC1
Update KA2, KB2, KC2
Update KA3, KB3, KC3
15-0
Coefficient Set Selected
DD
, the user should ensure that
PRODUCT SPECIFICATION
15-0
. Data
15-0
DO
.
after
1,0
on
7