AT89LP428-20MU ATMEL [ATMEL Corporation], AT89LP428-20MU Datasheet - Page 30

• Manufacturer Part Number: AT89LP428-20MU
• Description: 8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

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AT89LP428/828
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in
their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is
generated, the on-chip hardware clears the flag that generated it when the service routine is
vectored to. The Timer 2 Interrupt is generated by a logic OR of bits TF2 and EXF2 in register
T2CON. Neither of these flags is cleared by hardware when the CPU vectors to the service rou-
tine. The service routine normally must determine whether TF2 or EXF2 generated the interrupt
and that bit must be cleared by software.
The Serial Port Interrupt is generated by the logic OR of RI and TI in SCON. Neither of these
flags is cleared by hardware when the CPU vectors to the service routine. The service routine
normally must determine whether RI or TI generated the interrupt and that bit must be cleared by
software. The Serial Peripheral Interface Interrupt is generated by the logic OR of SPIF, MODF
and TXE in SPSR. None of these flags is cleared by hardware when the CPU vectors to the ser-
vice routine. The service routine normally must determine which bit generated the interrupt and
that bit must be cleared by software.
A logic OR of all eight flags in the GPIF register causes the GPI. None of these flags is cleared
by hardware when the service routine is vectored to. The service routine must determine which
bit generated the interrupt and that bit must be cleared in software. If the interrupt was level acti-
vated, then the external requesting source must de-assert the interrupt before the flag may be
cleared by software.
The CFA and CFB bits in ACSRA and ACSRB respectively generate the Comparator Interrupt.
The service routine must normally determine whether CFA or CFB generated the interrupt, and
the bit must be cleared by software.
A logic OR of the four least significant bits in the T2CCF register causes the Compare/Capture
Array Interrupt. None of these flags is cleared by hardware when the service routine is vectored
to. The service routine must determine which bit generated the interrupt and that bit must be
cleared in software.
All of the bits that generate interrupts can be set or cleared by software, with the same result as
though they had been set or cleared by hardware. That is, interrupts can be generated and
pending interrupts can be canceled in software.
Table 9-1.
Interrupt
System Reset
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port Interrupt
Timer 2 Interrupt
Analog Comparator Interrupt
General-purpose Interrupt
Compare/Capture Array Interrupt
Serial Peripheral Interface Interrupt
Interrupt Vector Addresses
Source
RST or POR or BOD
IE0
TF0
IE1
TF1
RI or TI
TF2 or EXF2
CFA or CFB
GPIF
T2CCF
SPIF or MODF or TXE
7-0
3-0
Vector Address
3654A–MICRO–8/09
0000H
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
004BH