AT89LP428-20MU ATMEL [ATMEL Corporation], AT89LP428-20MU Datasheet - Page 97

• Manufacturer Part Number: AT89LP428-20MU
• Description: 8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

17.5
Table 17-2.
Table 17-3.
Notes:
3654A–MICRO–8/09
SPDR Address = EAH
Not Bit Addressable
SPCR Address = E9H
Not Bit Addressable
Symbol
TSCK
SPE
DORD
MSTR
CPOL
CPHA
SPR0
SPR1
Bit
Bit
SPI Registers
1. Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE.
2. Enable the master SPI prior to selecting the slave device (SS low).
Writes to SPDR load the transmit buffer. In Master mode, a write also starts a transfer if the master is currently idle.
In Slave mode, if data is not loaded to SPDR the SPI will echo the last byte received on the next transfer. Reads
from SPDR return the value of the receive buffer, which is the last byte received. If SPDR is not read before
completion of the next transfer, the old value will be lost.
TSCK
SPD7
SCK Clock Mode. When TSCK = 0, the SCK baud rate is based on the system clock, divided by the SPR
TSCK = 1, the SCK baud rate is based on the Timer 1 overflow rate, divided by the SPR
SPI Enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and
P1.7. SPI = 0 disables the SPI channel.
Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.
Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects slave SPI mode.
Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not
transmitting. Please refer to
Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and
slave. Please refer to
SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no
effect on the slave. The relationship between SCK and the oscillator frequency, f
Function
SPR1
7
7
SPDR – SPI Data Register
SPCR – SPI Control Register
0
0
1
1
SPR0
0
1
0
1
SPD6
SPE
6
6
SCK (TSCK = 0)
f
f
f
f
OSC
OSC
OSC
OSC
Figure 23-9
/4
/8
/32
/64
Figure 23-9
DORD
SPD5
5
5
on SPI clock phase and polarity control.
SCK (TSCK = 1)
f
f
f
f
on SPI clock phase and polarity control.
T1OVF
T1OVF
T1OVF
T1OVF
MSTR
SPD4
/4
/8
/32
/64
4
4
SPD3
CPOL
3
3
Reset Value = 00H (after cold reset)
unchanged (after warm reset)
SPD2
CPHA
2
2
OSC.
, is as follows:
Reset Value = 0000 0000B
SPD1
1-0
SPR1
AT89LP428/828
1
1
ratio.
SPD0
SPR0
1-0
0
0
ratio.When
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