AT89LP428-20MU ATMEL [ATMEL Corporation], AT89LP428-20MU Datasheet - Page 92
AT89LP428-20MU
Manufacturer Part Number
AT89LP428-20MU
Description
8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT89LP428-20MU.pdf
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AT89LP428/828
Figure 17-1. SPI Block Diagram
The interconnection between master and slave CPUs with SPI is shown in
pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock
(SCK), and Slave Select (SS). The SCK pin is the clock output in master mode, but is the clock
input in slave mode. The MSTR bit in SPCR determines the directions of MISO and MOSI. Also
notice that MOSI connects to MOSI and MISO to MISO. By default SS/P1.4 is an input to both
master and slave devices.
In slave mode, SS must be driven low to select an individual device as a slave. When SS is held
low, the SPI is activated, and MISO becomes an output if configured by the user. All other pins
are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that
it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven
high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchro-
nous with the master clock generator. When the SS pin is driven high, the SPI slave will
immediately reset the send and receive logic, and drop any partially received data in the Shift
Register.The slave may ignore SS by setting its SSIG bit in SPSR. When SSIG = 1, the slave is
always enabled and operates in 3-wire mode. However, the slave output on MISO may still be
disabled by setting DISSO = 1.
T1 OVF
÷4/÷8/÷32/÷64
SPI Status Register
Oscillator
Select
Divider
1
0
SPI Control
TSCK
SPI Clock (Master)
SPI Interrupt
Request
MSTR
SPE
8
MSB
Data Bus
Internal
8
Read Data Buffer
Write Data Buffer
8-bit Shift Register
8
SPI Control Register
Clock
Logic
LSB
Figure
S
M
M
S
S
M
3654A–MICRO–8/09
17-2. The four
MISO
MOSI
P1.6
P1.5
SCK
P1.4
1.7
SS
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