AT89LP428-20MU ATMEL [ATMEL Corporation], AT89LP428-20MU Datasheet - Page 99

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AT89LP428-20MU

Manufacturer Part Number
AT89LP428-20MU
Description
8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Figure 18-1. Dual Comparator Block Diagram
3654A–MICRO–8/09
(P2.7) AIN3
(P2.6) AIN2
(P2.5) AIN1
(P2.4) AIN0
interrupt flag are not guaranteed to be stable for 10 µs. The corresponding comparator interrupt
should not be enabled during that time, and the comparator interrupt flag must be cleared before
the interrupt is enabled in order to prevent an immediate interrupt service. Before enabling the
comparators, the analog inputs should be tristated by putting P2.4, P2.5, P2.6 and P2.7 into
input-only mode. See
Each comparator may be configured to cause an interrupt under a variety of output value condi-
tions by setting the CMx
whenever the comparator outputs match the conditions specified by CMx
polled by software or may be used to generate an interrupt and must be cleared by software.
Both comparators share a common interrupt vector. If both comparators are enabled, the user
needs to read the flags after entering the interrupt service routine to determine which compara-
tor caused the interrupt.
The CAC
parator outputs. Normally, the outputs are sampled every clock system; however, the outputs
may also be sampled whenever Timer 0, Timer 1 or Timer 2 overflows. These settings allow the
comparators to be sampled at a specific time or to reduce the number of comparator events
seen by the system when using level sensitive modes. The comparators will continue to function
during Idle mode. If this is not the desired behavior, the comparators should be disabled before
entering Idle. The comparators are always disabled during Power-down mode.
1-0
CSB1
CSA1
CSB0
CSA0
and CBC
11
10
01
00
00
01
10
11
1-0
“Port 2 Analog Functions” on page
2-0
bits in AREF control when the comparator interrupts sample the com-
bits in ACSRx. The comparator interrupt flags CFx in ACSRx are set
11
10
01
00
00
01
10
11
RFB1
RFA1
RFB0
RFA0
B
A
V
V
V
AREF+Δ
AREF
AREF-Δ
CMB2
CMB1
CMB0
CMA2
CMA1
CMA0
38.
CFB
CFA
AT89LP428/828
CMPB (P4.7)
CMPA (P4.6)
EC
2-0.
The flags may be
Interrupt
99

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