ADM1027ARQZ-RL71 ONSEMI [ON Semiconductor], ADM1027ARQZ-RL71 Datasheet - Page 51

• Manufacturer Part Number: ADM1027ARQZ-RL71
• Manufacturer: ONSEMI [ON Semiconductor]

REV. A
Register Address
0x6F
<0>
<7:1>
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
Register Address
0x70
<7:0>
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
Register Address
0x71
<7:0>
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
Register Address
0x72
<7:0>
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
Read/Write
XEN
Reserved
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
R/W
R/W
R/W
R/W
Table XXVII. Remote 2 Temperature Offset
XOR Tree Test Enable Register
If the XEN bit is set to 1, the device enters the XOR tree test mode. Clearing the bit
Unused. Do not write to these bits.
Remote 1 Temperature Offset
Allows a twos complement offset value to be automatically added to or subtracted from
Local Temperature Offset
Allows a twos complement offset value to be automatically added to or subtracted from
Remote 2 Temperature Offset
Allows a twos complement offset value to be automatically added to or subtracted from
Description
removes the device from the XOR tree test mode.
Description
the Remote 1 temperature reading. This is to compensate for any inherent system offsets
such as PCB trace resistance. LSB value = 1
Description
the local temperature reading. LSB value = 1
Description
the Remote 2 temperature reading. This is to compensate for any inherent system off-
sets such as PCB trace resistance. LSB value = 1
Table XXV. Remote 1 Temperature Offset
Table XXVI. Local Temperature Offset
Rev. 3 | Page 51 of 56 | www.onsemi.com
Table XXIV. XOR Tree Test Enable
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o
Power-On Default
0x00
Power-On Default
0x00
Power-On Default
0x00
Power-On Default
0x00
C.
o
C.
o
C.
ADM1027