HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 349
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HD64570
Manufacturer Part Number
HD64570
Description
Serial Communications Adaptor
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD64570.pdf
(469 pages)
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9.1.4
Initialization: An example of an initialization program is given below.
CMD fl 21H........................................ Resets channel.
MD0
MD2
CTL
TRC0 fl 1FH........................................ TXRDY bit = 1 when the transmit buffer is not full.
TRC1 fl 1FH........................................ TXRDY bit = 0 when the transmit buffer is full.
fl 87H........................................ Specifies bit synchronous HDLC mode.
fl 00H........................................ Specifies the NRZ code.
fl 11H........................................ Specifies idle pattern transmission.
Transmission in DMA Chained-Block Transfer Mode (Bit Synchronous HDLC
Mode)
Figure 9.4 RXINT Interrupt Processing Routine (using HD64180)
Analyze interrupt source
Read ST1 and ST2
(ACC
Issue EI instruction
Process interrupt
Clear interrupt
(ST2
ST1
source bit
Return
Start
ST1, ST2)
ACC)
ACC,
Specifies CRC-CCITT mode, and presets to all 1s.
Specifies full-duplex mode.
Specifies RTS line high-level output.
ACC:
ST1:
ST2:
Accumulator
Status register 1
Status register 2
Rev. 0, 07/98, page 333 of 453
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