HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 388
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HD64570
Manufacturer Part Number
HD64570
Description
Serial Communications Adaptor
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD64570.pdf
(469 pages)
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Table 10.34 CPU Mode 1 Master Mode Bus Timing
(V
Item
Clock cycle time
Clock high-level pulse width
Clock low-level pulse width
Clock fall time
Clock rise time
Address delay time
Address set-up time
AS delay time 1
RD delay time 1
Address hold time
AS delay time 2
RD delay time 2
Data read set-up time
Data read hold time
WAIT set-up time
WAIT hold time
Write data floating delay time
WR delay time 1
Write data delay time
Write data set-up time
WR delay time 2
WR pulse width
Write data hold time
AS high-level pulse width
AS low-level pulse width
Rev. 0, 07/98, page 372 of 453
CC
= 5 V
10%, V
SS
= 0 V, Ta = 40 to +85 C unless otherwise specified)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC
CHW
CLW
cf
cr
AD
AS
ASD1
RDD1
AH
ASD2
RDD2
DRS
DRH
WS
WH
WDZ
WRD1
WDD
WDS
WRD2
WRP
WDH
ASWH
ASWL
Min
125
50
50
20
10
25
5
30
30
15
110
10
70
80
Typ
Max
2000
10
10
55
50
50
50
50
60
50
60
55
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing
Figure 10.7
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