CS8403A-CS CIRRUS [Cirrus Logic], CS8403A-CS Datasheet
CS8403A-CS
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CS8403A-CS Summary of contents
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... ORDERING INFO CS8403A-CS °C, 24-pin Plastic SOIC CS8404A-CS °C, 24-pin Plastic SOIC This document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice. ...
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... TABLE OF CONTENTS: GENERAL DESCRIPTION ..................................................................................................... 8 Line Drivers ........................................................................................................................ 8 CS8403A DESCRIPTION ........................................................................................................ 8 Parallel Port ......................................................................................................................... 8 Status and Control Registers ............................................................................................... 8 Serial Port.......................................................................................................................... 11 Buffer Memory.................................................................................................................. 12 Buffer Mode 0 ............................................................................................................. 13 Buffer Mode 1 ............................................................................................................. 14 Buffer Mode 2 ............................................................................................................. 15 Buffer-Read and Interrupt Timing .................................................................................... 15 PIN DESCRIPTIONS ............................................................................................................. 17 Power Supply Connections ......................................................................................... 17 Audio Input Interface .................................................................................................. 17 Parallel Interface ......................................................................................................... 17 Transmitter Interface ...
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... Master Clock Frequency Master Clock Duty Cycle Notes: 4. MCK for the CS8403A must be 128, 192, 256, or 384x the input word rate based on M0 and M1 in control register 2. MCK for the CS8404A must be 128x the input word rate, except in Transparent Mode where MCK is 256x the input word rate. ...
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... DIGITAL CHARACTERISTICS - RS422 DRIVERS Parameters Output High Voltage Output Low Voltage SWITCHING CHARACTTERISTICS - CS8403A PARALLEL PORT VD+ = 5V, Inputs: Logic0 = GND, Logic1 = VD+, C Parameters ADDRESS valid to CS low CS high to ADDRESS invalid RD/WR valid to CS low CS low to RD/WR invalid CS low DATA valid to CS rising CS high to DATA invalid ...
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... The diagrams show SBC rising coincident with the first rising edge of SCK after FSYNC transitions. This is true for all modes except FSF0 & 1 both equal 1 in the CS8403A, and format 4 in the CS8404A. In these modes SBC is delayed one full SCK period. ...
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... Processor or Microcontroller sfds sfs SCK t sss t css C,U uss SBC External Clock 5 MCK 7 FSYNC 6 SCK 8 SDATA CS8403A 15 INT RD/WR A0-A4 D0-D7 Figure 1. CS8403A Typical Connection Diagram CS8403A CS8404A t sckf t ssh t sch t suh +5V 19 VD+ 0.1 µF 18 GND 20 Transmitter TXP Circuit 17 TXN See Appendix B DS239PP1 ...
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... MCK 7 FSYNC VD+ 6 SCK 8 SDATA GND 9 V CS8404A 10 SBF SBC M0 16 RST TXP 8 Dedicated C.S. Bits TXN CS8403A CS8404A +5V 0.1 µ Serial Port 22 Mode Select 21 20 Transmitter Circuit 17 See Appendix B +5V 19 0.1 µ Serial Port 22 Mode Select 21 20 Transmitter Circuit ...
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... RS422 line driver. A block diagram of the CS8403A is shown in Figure 4. In accordance with the professional definition of channel status, the CRCC code (C.S. byte 23) can be internally generated ...
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... Validity Preamble Parity Figure 4. CS8403A Block Diagram CS8403A is set so that three frame delays occur from the input of the CS8413 to the output of the CS8403A. In Transparent Mode, 32 SCKs are re- quired per subframe. Channel status block alignment between the CS8413 and the CS8403A is accomplished by set- ting BKST high at the occurrence of the Flag 2 ris- ing edge of the CS8413 ...
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... Memory Mode Figure 5. CS8403A Buffer Memory Modes B0 select one of three modes for the buffer memo- ry. The different modes are shown in Figure 5 and the bit combinations in Table 2. More information on the different modes can be found in the Buffer Memory section. Bit 2, CRCE, is the channel sta- tus CRCC enable and should only be used in pro- fessional mode ...
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... When RST is low, the differential line drivers are set to ground and the block counters are reset to the beginning of the first block. In order to properly synchronize the rest of the CS8403A to the audio serial port, the transmit timing counters, which in- clude the flags in the status register, are not enabled ...
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... FSYNC must be derived from MCK via a DSP us- ing the same clock or by external counters. If FSYNC moves (jitters) with respect to MCK by more than 4 MCK periods, the CS8403A may reset the channel status block and flags. Appendix C contains more information on the relationship of FSYNC and MCK. ...
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... Channel Status Byte (Expanded (Expanded) Sub-frame 7 8 Aux Data LSB Audio Data Figure 11. CS8403A Status Register Flag Timing CS8403A CS8404A MSB Validity User Data Channel Status Data Parity Bit ...
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... User Address Figure 12. CS8403A Buffer Momory Read Sequence - MODE 0 14 tions 08H to 0FH, is divided into two sections. The first four locations always contain the first four bytes of channel status, identical to mode 0, and are read once per channel status block. The second four locations, addresses 0CH to 0FH, provide a cyclic buffer for the last 20 bytes of channel status data ...
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... Aux. Address 10 13, Figure 13. CS8403A Buffer Memory Read Sequence - MODE 1 Buffer Mode 2 In buffer mode 2, two 8-byte buffers are available for buffering both channel A and channel B chan- nel status data independently. Both buffers are identical to the channel status buffer in mode 1 ex- cept that each channel can have unique channel sta- tus data ...
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... Right C.S. Ad Flag 1 Flag 0 Left C.S. Ad Right C.S. Ad User Address Figure 14. CS8403A Buffer Memory Read Sequence - MODE 2 IMCK (128Fs) Flags 0 & 1 Flag 2 INT RAM Read TXP C TXN Figure 15. RAM/Buffer-Read and Interrupt Timing 16 Block (384 Audio Samples ...
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... SDATA TXN RD/ INT CS8403A CS8404A DATA BUS BIT 3 DATA BUS BIT 2 DATA BUS BIT 1 DATA BUS BIT 0 TRANSMIT POSITIVE POWER GROUND TRANSMIT NEGATIVE READ/WRITE SELECT INTERRUPT CHIP SELECT ADDRESS BUS BIT 0 17 ...
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... Clock input which defines the transmit timing. It can be configured, via control register 2, for 128, 192, 256, or 384 times the sample rate. TXP, TXN - Differential Line Drivers, PINS 20, 17. RS422 compatible line drivers. Drivers are pulled low when part is in reset state. 18 CS8403A CS8404A resistor to DS239PP1 ...
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... Figure 16. Format 0 and 1 are de- signed to interface with Crystal ADCs. Format 2 communicates with Motorola and TI DSPs. Format 3 is reserved. Format 4 is compatible with DS239PP1 CS8403A CS8404A 2 the I S standard. Formats 5 and 6 make the CS8404A look similar to existing 16- and 18-bit DACs, and interpolation filters ...
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... MSB LSB Left MSB LSB Left LSB MSB 16 Bits Left LSB MSB 18 Bits Left MSB LSB Figure 16. CS8404A Audio Serial Port Formats CS8403A CS8404A Right MSB LSB Right MSB LSB Right MSB LSB Right MSB LSB Right LSB MSB 16 Bits Right ...
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... C bit OR’ pin Left 0 Right 0 VUCP0L VUCP0R Preamble Z Preamble LSB Left 0 - Audio Data Sub-frame Figure 17. CBL and Tranmitter Timing CS8403A CS8404A Right 128 Left 0 CUV128R CUV0L CUV128L CUV191R Bit 0 of C.S. Block Byte 16 Left 128 Right 128 VUCP127R VUCP128L Preamble X ...
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... CBL returns low one bit period before the start of the frame that contains bit 0 of channel status byte 16. CBL is the exact inverse of flag 1 in mode 0 on the CS8403A (see Figure 11). CBL is not available when the CD subcode port is enabled. ...
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... C pin. EM1 Audio Serial Port Logic Aux C Bits CRC U Bits Validity Preamble Parity CS8403A CS8404A EM0 Table 4. Emphasis Encoding 20 Biphase Line Mark 17 Driver Encoder ...
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... FC1 Audio Serial Port Logic Aux C Bits U Bits Validity Preamble Parity C15 CS8403A CS8404A FC0 C24 C25 Comments 44.1 kHz 48.0 kHz 32.0 kHz 44.1 kHz, CD Mode Table 5. Sample Frequency Encoding Biphase Line ...
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... Channel status bits are set by the dedicated pins; the category code is forced to CD Audio Serial Port Logic Aux C Bits Port U Bits Validity Preamble Parity C15 CS8403A CS8404A Biphase Line Mark Driver Encoder Mux Timing 5 MCK 20 TXP 17 TXN 16 RST 25 ...
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... SBF U SBC SBF Data latched on rising edge SBC Figure 22. CD Subcode Port Timing CS8403A CS8404A (Expanded) W DS239PP1 ...
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... C/SBF CBL/SBC EM0/C9 C9/C15 EM1/ CS8403A CS8404A TRANSPARENT / FREQ. CTRL. 1 SERIAL PORT MODE SELECT 2 SERIAL PORT MODE SELECT 1 SERIAL PORT MODE SELECT 0 TRANSMIT POSITIVE POWER GROUND TRANSMIT NEGATIVE MASTER RESET CS BLOCK OUT / SC BIT CLOCK EMPHASIS BIT 9 EMPHASIS BIT 8 ...
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... In professional mode the inverse of channel status bit 1. In consumer mode, FC0 and FC1 are encoded versions of channel status bits 24 and 25 (bits 0 and 1 of byte 3). When FC0 and FC1 are both high, CD mode is selected. C1/FC0 are ignored in Transparent Mode. 28 CS8403A CS8404A DS239PP1 ...
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... MCK - Master Clock, PIN 5. Clock input at 128x Fs the sample frequency which defines the transmit timing. In transparent mode, MCK must be 256x Fs. TXP, TXN - Differential Line Drivers, PINS 20, 17. RS422 compatible line drivers. Drivers are pulled to low when part is in reset state. DS239PP1 CS8403A CS8404A 29 ...
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... APPENDIX A: RS422 DRIVER INFORMATION The RS422 drivers on the CS8403A and CS8404A are designed to drive both the professional and con- sumer interfaces. The AES/EBU specification for professional/broadcast use calls for a 110 impedance and a balanced drive capability. Since the transmitter impedance is very low, a 110 sistor should be placed in series with one of the transmit pins ...
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... R1. PLD is an internal signal that parallel loads R1 into the R2 buffer, and, at the same time, the C, U, and V bits are latched. On the CS8403A, the C, U, and V bits are held in RAM, whereas on the CS8404A, they are latched from ex- ternal pins. The PLD signal rises on the first SCK edge that can latch data ...
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... SDATA SCK Internally generated P C CS8404A Port CS8403A Internal Memory IMCK 2 Figure B1. Serial Port-to-Transmitter Block Diagram 9.5 SCK FSYNC SDATA CS8404A CUV191R PLD IMCK LDS TXP Left 191 TXN CS8403A Flags CS8404A CBL Figure B2. Serial Port-to-Transmitter Timing (slave mode) ...
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SOIC (300 MIL BODY) PACKAGE DRAWING 1 b SEATING PLANE e DIM MIN A 0.093 A1 0.004 B 0.013 C 0.009 D 0.598 E 0.291 e 0.040 H 0.394 L 0.016 0° INCHES MILLIMETERS MAX ...