CS8403A-CS CIRRUS [Cirrus Logic], CS8403A-CS Datasheet - Page 31

• Manufacturer Part Number: CS8403A-CS
• Description: 96KHZ DIGITAL AUDIO TRANSMITTER
• Manufacturer: CIRRUS [Cirrus Logic]

[phone]
Part Number: PE65612
Schott Corporation
1000 Parkers Lane Rd.
Wayzata, MN 55391
[phone]
FAX [phone]
Part Number:
Scientific Conversions Inc.
42 Truman Drive
Novato, CA. 94947
[phone]
Part Number:
APPENDIX B: MCK AND FSYNC
RELATIONSHIP
FSYNC should be derived either directly or indi-
rectly from MCK. The indirect case could be a
DSP, providing FSYNC through its serial port, us-
ing the same master oscillator that generates MCK.
In either case, FSYNC’s relationship to MCK is
fixed and does not move. Since this appendix pro-
vides information on what would happen if
FSYNC did move with respect to MCK, it does not
apply to the majority of users.
All internal timing is derived from MCK. On the
CS8404A, MCK is always 128xFs. On the
CS8403A, the external MCK is programmable and
is initially divided to 128xFs before being used by
the part. The internal clock IMCK used in the fol-
lowing discussion is always 128xFs regardless of
the external MCK pin.
After RST, the CS8403A and CS8404A synchro-
nize the internal timing to the audio data port, more
specifically FSYNC, to guarantee that channel A is
DS239PP1
67125450 - compatible with Pulse
67128990 - lower cost
67129000 - surface mount
67129600 - single shield
SC916-01 - single shield
SC916-02 - surface mount
left channel data and channel B is right channel
data as per the AES/EBU specification. If FSYNC
moves with respect to IMCK, the transmitter could
lose synchronization, which causes an internal re-
set.
Figure B1 shows the structure of the serial port in-
put, to the transmitter output. The audio data is se-
rially shifted into R1. PLD is an internal signal that
parallel loads R1 into the R2 buffer, and, at the
same time, the C, U, and V bits are latched. On the
CS8403A, the C, U, and V bits are held in RAM,
whereas on the CS8404A, they are latched from ex-
ternal pins. The PLD signal rises on the first SCK
edge that can latch data. This is coincident with the
latching of the MSB of audio data in MSB-first,
left-justified modes. PLD stays high for one SCK
period. In the CS8404A section, the arrows on SCK
in Figure 16 indicate when PLD goes high. Also,
SBC in the CS8404A CD submode is an external
version of PLD gated by the SBF input.
When the part is finished transmitting the preamble
of a sub-frame, the internal signal LDS rises to par-
allel-load R2 into R3 for transmission. After RST,
the part synchronizes the audio port to IMCK as
shown in Figure B2. Since PLD is based on
FSYNC and LDS is based on IMCK, if FSYNC
moves with respect to IMCK until PLD and LDS
occur at the same time, the data would not be prop-
erly loaded into R3. If LDS and PLD overlap, an
internal reset is initiated causing the timing to re-
turn to the initial state shown in Figure B2.
CS8403A CS8404A
31