CS8403A-CS CIRRUS [Cirrus Logic], CS8403A-CS Datasheet - Page 22

• Manufacturer Part Number: CS8403A-CS
• Description: 96KHZ DIGITAL AUDIO TRANSMITTER
• Manufacturer: CIRRUS [Cirrus Logic]

channel status block is transmitted. This sub-frame
contains channel status byte 0, bit 0. CBL returns
low one bit period before the start of the frame that
contains bit 0 of channel status byte 16. CBL is the
exact inverse of flag 1 in mode 0 on the CS8403A
(see Figure 11). CBL is not available when the CD
subcode port is enabled.
Figure 17 illustrates timing for stereo data input on
the audio port. Notice how CBL rises while the
right channel data (Right 0) is input, but the previ-
ous left channel data (Left 0) is being transmitted as
the first sub-frame of the channel status block
(starting with preamble Z). The C, U, and V input
ports only need to be valid for a short period after
FSYNC changes. A sub-frame includes one audio
sample while a frame includes a stereo pair. A
channel status (C.S.) block contains 24 bytes of
channel status and 384 audio samples (or 192 ste-
reo pairs, or frames, of samples).
Figure 17 shows the CUV ports as having left and
right bits (e.g. CUV0L, CUV0R). Since the C.S.
block is defined as 192 bits, or one bit per frame,
there are actually 2 C.S. blocks, one for channel A
(left) and one for channel B (right). When inputting
stereo audio data, both blocks normally contain the
same information, so C0L and C0R from the input
port pin are both channel status bit 0 of byte 0,
which is defined as professional/consumer. These
first two bits from the port, C0L and C0R, are log-
ically OR’ed with the inverse of PRO, since PRO is
a dedicated channel status pin defined as C.S. bit 0.
Also, if in professional mode, C1, C6, C7 and C9
are dedicated C.S. pins. The inverse of C1 is logi-
cally OR’ed with channel status input port bits C1L
and C1R. In similar fashion, C6, C7 and C9 are
OR’ed with their respective input bits. Also, the C
bits in CUV128L and CUV128R are both channel
status block bit 128, which is bit 0 of channel status
byte 16.
22
Transparent Mode
In certain applications it is desirable to receive dig-
ital audio data with the CS8414 and retransmit
with the CS8404A. In this case, channel status, user
and validity information must pass through unal-
tered. For studio environments, AES recommends
that signal timing synchronization be maintained
throughout the studio. Frame synchronization of
digital audio signals input to and output from a
piece of equipment must be within ±5%.
The transparent mode of the CS8404A is selected
by setting TRNPT (pin 24) high. In this mode, the
CBL pin becomes an input, allowing direct connec-
tion of the outputs of the CS8414 to the inputs of
the CS8404A as shown in Figure 18. The transmit-
ter and receiver are synchronized by the FSYNC
signal. CBL specifies the start of a new channel sta-
tus block boundary, allowing the transmit block
structure to be slaved to the block structure of the
receiver. In the transparent mode, C, U, and V are
now transmitted with the current audio sample as
shown in Figure 17 (TRNPT high) and the dedicat-
ed channel status pins are ignored. When in the
transparent mode, the propagation delay of data
through the CS8404A is set so that the total propa-
gation delay from the receive inputs of the CS8414
to the transmit outputs of the CS8404A is three
frames.
Figure 18. Transparent Mode Interface
RXP
RXN
CS8414
CS8403A CS8404A
Processing
FSYNC
SDATA
MCK
SCK
Data
CBL
C
U
V
CS8404A
TRNPT
TXN
TXP
DS239PP1
V+