CS8403A-CS CIRRUS [Cirrus Logic], CS8403A-CS Datasheet - Page 15

• Manufacturer Part Number: CS8403A-CS
• Description: 96KHZ DIGITAL AUDIO TRANSMITTER
• Manufacturer: CIRRUS [Cirrus Logic]

Buffer Mode 2
In buffer mode 2, two 8-byte buffers are available
for buffering both channel A and channel B chan-
nel status data independently. Both buffers are
identical to the channel status buffer in mode 1 ex-
cept that each channel can have unique channel sta-
tus data. The two buffers are read simultaneously
with locations 08H to 0FH transmitted in channel A
and locations 10H to 17H transmitted in channel B.
Figure 5 contains the buffer memory modes and
Figure 14 illustrates the buffer read sequence for
mode 2.
Buffer-Read and Interrupt Timing
As mentioned previously in the buffer mode sec-
tions, conflicts between externally writing to the
buffer ram and the CS8403A internally reading
bytes of ram for transmission may be averted by us-
ing the flag levels to avoid the section currently be-
DS239PP1
C.S. Address
User Address
C.S. Byte
C.S. Address
Aux. Address
Flag 2
Flag 1
Flag 0
Flag 1
Flag 0
08
08
04
10
0
1
13,14
2
05
Figure 13. CS8403A Buffer Memory Read Sequence - MODE 1
3
0B 0C
4
17 18
5
09
06
6
1B,1C
7
0F 0C
07
8
(384 Audio Samples)
9
1F 10
10 11 12 13 14 15 16 17 18 19 20 21 22 23 0
0A
04
Block
0F 0C
ing addressed by the part. Interrupts occur at flag
edges indicating the exact byte that the part is cur-
rently reading. Utilizing INT along with the flags,
the byte currently being read by the part can be
avoided allowing access to all other bytes instead
of just a section. Figure 15 illustrates the timing be-
tween flags, INT, and the internal reading of the
buffer for transmission. The master clock IMCK is
shown as 128x Fs. Other MCK frequencies are ini-
tially divided to obtain 128x Fs, defined as IMCK
(internal MCK), which is then used for all internal
timing, so the timing in Figure 15 is valid for all
MCK frequencies. When the parity bit (P) is trans-
mitted, a transition on a flag causes INT to go low
if the appropriate mask bit is set. Concurrently, the
part starts reading from the internal buffer. Writing
to the buffer ram location being read by the part
should be avoided while the internal "ram read"
signal is high.
13,14
(Expanded)
05
17 18
0F 0C
06
0B
1B,1C
CS8403A CS8404A
07
0F 0C
(Addresses are in Hex)
1F
0F 08
1
15