CS8403A-CS CIRRUS [Cirrus Logic], CS8403A-CS Datasheet - Page 24

• Manufacturer Part Number: CS8403A-CS
• Description: 96KHZ DIGITAL AUDIO TRANSMITTER
• Manufacturer: CIRRUS [Cirrus Logic]

The channel status data cyclic redundancy check
character (C.S. byte 23) is always generated inde-
pendently for channels A and B and is transmitted
at the end of the channel status block.
Data should not be input through the channel status
port, C, during the CRCC byte time frame, since in-
puts on C are logically OR’ed with internally gen-
erated data.
Consumer Mode
Setting PRO high places the CS8404A in consumer
mode which redefines the pins as shown in Figure
20. In consumer mode, channel status bit 0 is trans-
mitted as a zero and channel status bits 2, 3, 8, 9,
15, 24, and 25 are controlled via dedicated pins.
The pins are actually the inverse of the bit so if pin
C2 is tied high, channel status bit 2 will be trans-
mitted as a zero. Also, FC0 and FC1 are encoded
versions of channel status bits 24 and 25, which de-
fine the sample frequency. When FC0 and FC1 are
24
FSYNC
SDATA
+5V
SCK
C
U
V
PRO
8
6
7
10
11
9
2
Registers
FC0
3
FC1
24
C2
4
Figure 20. CS8404A Block Diagram - Consumer Mode
M2 M1 M0
C3
23 22 21
Serial
Logic
Port
1
C8
13
C9
14
C15
12
Preamble
Validity
C Bits
U Bits
Audio
Parity
Aux
both high, the part is placed in a CD submode
which activates the CD subcode port. This sub-
mode is described in detail in the next section. Ta-
ble 5 describes the encoding of C24 and C25
through the FC1 and FC0 pins. According to AES/
EBU standards, C2 is copy prohibit/permit, C3
specifies pre-emphasis, C8 and C9 define the cate-
gory code, and C15 identifies the generation status
of the transmitted material (i.e. first generation,
second generation).
FC1
0
0
1
1
Table 5. Sample Frequency Encoding
FC0
Mux
0
1
0
1
C24
0
0
1
0
CBL
Encoder
Biphase
Timing
15
Mark
CS8403A CS8404A
MCK
C25
0
1
1
0
5
44.1 kHz
48.0 kHz
32.0 kHz
44.1 kHz, CD Mode
Driver
Line
Comments
DS239PP1
20
17
16
TXP
TXN
RST