CS8403A-CS CIRRUS [Cirrus Logic], CS8403A-CS Datasheet - Page 21

• Manufacturer Part Number: CS8403A-CS
• Description: 96KHZ DIGITAL AUDIO TRANSMITTER
• Manufacturer: CIRRUS [Cirrus Logic]

C, U, V Serial Port
The serial input pins for channel status (C), user
(U), and validity (V) are sampled during the first bit
period after the active edge of FSYNC for all for-
mats except Format 4. Format 4 is sampled during
the second bit period (coincident with the MSB). In
Figure 16, the arrows on SCK indicate when the C,
U, and V bits are sampled. The C, U, and V bits are
transmitted with the audio sample entered before
the FSYNC edge that sampled it. The V bit, as de-
fined in the audio standards, is set to zero to indi-
cate the audio data is suitable for conversion to
analog. Therefore, when the audio data is errorred,
or the data is not audio, the V bit should be set high.
The channel status serial input pin (C) is not avail-
able in consumer mode when the CD subcode port
is enabled (FC1 = FC0 = high). Any channel status
data entered through the channel status serial input
(C) is logically OR’ed with the data entered
through the dedicated pins or internally generated.
DS239PP1
CBL
SDATA
FSYNC
C,U,V
TXP
TXN
TRNPT high
TRNPT high
TRNPT low
TRNPT low
bit
0
Preamble Z
C bits OR’ed w/
PRO pin
CUV0L
CUV191R
Left 0
Preamble Y
3 4
VUCP191R
Right 191
Aux Data
C bits from Cpin
CUV0R
CUV0L
7
Right 0
8
Preamble Z
LSB
Figure 17. CBL and Tranmitter Timing
Left 0
VUCP0L
CUVIL
CUV0R
C bit OR’ed w/
C1 pin
Left 1
Preamble Y
Right 0
VUCP0R
Sub-frame
Left 0 - Audio Data
RST and CBL (TRNPT is low)
When RST goes low, the differential line drivers
are set to ground and the block counters are reset to
the beginning of the first block. In order to properly
synchronize the CS8404A to the audio serial port,
the transmit timing counters, which include CBL,
are not enabled after RST goes high until eight and
one half SCK periods after the active edge (first
edge after reset is exited) of FSYNC. When
FSYNC is configured as a left/right signal (all de-
fined formats except 2), the counters and CBL are
not enabled until the right sample is being entered
(during which the previous left sample is being
transmitted). This guarantees that channel A is left
and channel B is right as per the digital audio inter-
face specs.
As shown in Figure 17, channel block start output
(CBL), can assist in serially inputting the C, U and
V bits as CBL goes high one bit period before the
first bit of the preamble of the first sub-frame of the
CUV1L
CUV1R
Left 128
VUCP127R
Bit 0 of C.S.
Block Byte 16
CUV128R
CUV128L
Right 128
Preamble X
VUCP128L
CS8403A CS8404A
Left 128
MSB
27
V0
28 29 30 31
CUV0L
CUV191R
U0
Preamble Y
Left 0
Right 128
C0
P0
Right 0
CUV0R
CUV0L
21