CS8415A-IZ CIRRUS [Cirrus Logic], CS8415A-IZ Datasheet - Page 19

• Manufacturer Part Number: CS8415A-IZ
• Description: 96 kHz DIGITAL AUDIO INTERFACE RECEIVER
• Manufacturer: CIRRUS [Cirrus Logic]

7. CONTROL PORT REGISTER SUMMARY
7.1
Note:
(HEX)
Addr
14-1D
20-37
0A
0B
0C
0D
0E
1E
01
02
04
06
07
08
09
0F
10
12
13
7F
11
INCR
7
Memory Address Pointer (MAP)
INCR - Auto Increment Address Control Bit
MAP6:MAP0 - Register address
Reserved registers must not be written to during normal operation. Some reserved registers are used for
test modes, which can completely alter the normal operation of the CS8415A.
Control 1
Control 2
Clock Source Control
Serial Output Format
Interrupt 1 Status
Interrupt 2 Status
Interrupt 1 Mask
Interrupt 1 Mode (MSB)
Interrupt 1 Mode (LSB)
Interrupt 2 Mask
Interrupt 2 Mode (MSB)
Interrupt 2 Mode (LSB)
Receiver CS Data
Receiver Errors
Receiver Error Mask
CS Data Buffer Control
U Data Buffer Control
Q sub-code Data
OMCK/RMCK Ratio
C or U Data Buffer
ID and Version
Default = ‘0’
0 - Disabled
1 - Enabled
Function
MAP6
6
MAP5
SWCLK
SOMS
ORR7
AUX3
5
ID3
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 1. Control Register Map Summary
OSLIPM
QCRCM
OSLIP1
OSLIP0
HOLD1
OSLIP
QCRC
SOSF
ORR6
AUX2
RUN
ID2
6
0
0
0
0
0
0
0
MAP4
4
MUTESAO
SORES1
CCRCM
HOLD0
CCRC
ORR5
AUX1
BSEL
ID1
5
0
0
0
0
0
0
0
0
0
0
MAP3
3
UNLOCKM
UNLOCK
SORES0
RMCKF
CBMR
ORR4
AUX0
ID0
4
0
0
0
0
0
0
0
0
0
0
0
SOJUST
DETUM
MAP2
DETU1
DETU0
DETCI
DETU
ORR3
VER3
MMR
PRO
VM
2
3
0
0
0
0
V
0
0
0
CONFM
DETCM
SODEL
DETC1
DETC0
AUDIO
MUX2
CONF
ORR2
DETC
VER2
INT1
2
0
0
0
0
0
0
0
MAP1
1
SOSPOL
QCHM
DETUI
COPY
MUX1
QCH1
QCH0
ORR1
VER1
BIPM
QCH
CAM
INT0
BIP
1
0
0
0
0
0
CS8415A
SOLRPOL
MAP0
RERRM
RERR1
RERR0
MUX0
RERR
PARM
ORR0
ORIG
VER0
CHS
PAR
0
0
0
1
0
0
0
0
0
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