CS8415A-IZ CIRRUS [Cirrus Logic], CS8415A-IZ Datasheet - Page 38

• Manufacturer Part Number: CS8415A-IZ
• Description: 96 kHz DIGITAL AUDIO INTERFACE RECEIVER
• Manufacturer: CIRRUS [Cirrus Logic]

15. APPENDIX B: CHANNEL STATUS AND
15.1
The CS8415A contains sufficient RAM to store a
full block of C data for both A and B channels (192
x 2 = 384 bits), and also 384 bits of U information.
The user may read from these buffer RAMs
through the control port.
The buffering scheme involves 2 block-sized buff-
ers, named D and E, as shown in Figure 15. The
MSB of each byte represents the first bit in the se-
rial C data stream. For example, the MSB of byte 0
(which is at control port address 20h) is the con-
sumer/professional bit for channel status block A.
The first buffer (D) accepts incoming C data from
the AES receiver. The 2nd buffer (E) accepts entire
blocks of data from the D buffer. The E buffer is
also accessible from the control port, allowing
reading of the C data.
15.2
The user can monitor the incoming data by reading
the E buffer, which is mapped into the register
space of the CS8415A, through the control port.
38
From
AES3
Receiver
USER DATA BUFFER MANAGEMENT
Figure 15. Channel Status Data Buffer Structure
AES3 Channel Status (C) Bit
Management
Accessing the E buffer
Received
Data
Buffer
D
8-bits
A
Control Port
words
E
8-bits
24
B
The user can configure the interrupt enable regis-
ter to cause interrupts to occur whenever D to E
buffer transfers occur. This allows determination of
the allowable time periods to interact with the E
buffer.
Also provided is a D to E inhibit bit. This may be
used whenever “long” control port interactions are
occurring.
A flowchart for reading the E buffer is shown in
Figure 16. Since a D to E interrupt just occurred af-
ter reading, there is a substantial time interval until
the next D to E transfer (approximately 24 frames
worth of time). This is usually plenty of time to ac-
cess the E data without having to inhibit the next
transfer.
15.2.1 Reserving the first 5 bytes in the E
D to E buffer transfers periodically overwrite the
data stored in the E buffer. The CS8415A has the
capability of reserving the first 5 bytes of the E buff-
er for user writes only. When this capability is in
use, internal D to E buffer transfers will NOT affect
the first 5 bytes of the E buffer. Therefore, the user
can set values in these first 5 E bytes once, and the
settings will persist until the next user change. This
mode is enabled using the Channel Status Data
Buffer Control register.
D to E interrupt occurs
Return
Figure 16. Flowchart for Reading the E Buffer
buffer
Optionally set D to E inhibit
If set, clear D to E inhibit
Read E data
CS8415A