CS8415A-IZ CIRRUS [Cirrus Logic], CS8415A-IZ Datasheet - Page 31

• Manufacturer Part Number: CS8415A-IZ
• Description: 96 kHz DIGITAL AUDIO INTERFACE RECEIVER
• Manufacturer: CIRRUS [Cirrus Logic]

11. PIN DESCRIPTION - HARDWARE MODE
COPY
VL2+
VL+
VL3+
EMPH
RXP0
RXN0
VA+
AGND
FILT
RST
RMCK
RERR
23
27
10
11
1
2
3
4
5
6
7
8
9
COPY Channel Status Bit (Output)
ing AES3 data stream. If the category code is set to General, copyright will be indicated whatever the
state of the Copyright bit.
Positive Digital Power (Input) - Typically +3 to +5V.
Pre-Emphasis (Output) - EMPH is low when the incoming Channel Status data indicates 50/15 µs pre-
emphasis. EMPH is high when the Channel Status data indicates no pre-emphasis or indicates pre-
emphasis other than 50/15 µs. This pin is also a start-up option which, along with ORIG, determines the
serial port format. A 47 kΩ resistor to either VL+ or DGND is required.
AES3/SPDIF Receiver Port (Input) - Differential line receiver inputs for the AES3 biphase encoded data.
See Appendix A for recommended circuits.
Positive Analog Power (Input) - Nominally +5 V. This supply should be as quiet as possible since noise
on this pin will directly affect the jitter performance of the recovered clock.
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-
nected to a common ground area under the chip.
PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. See
“Appendix C: PLL Filter” on page 40 for recommended schematic and component values.
Reset (Input) - When RST is low, the CS8415A enters a low power mode and all internal states are
reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are
stable in frequency and phase. This is particularly true in hardware mode with multiple CS8415A devices
where synchronization between devices is important.
Recovered Master Clock (Output) - Recovered master clock output when PLL is locked to the incoming
AES3 stream. Frequency is 256x the sample rate (Fs).
Receiver Error (Output) - When high, indicates an error condition in the AES3 receiver. The status of
this pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to go
high are: validity bit high, parity error, bi-phase coding error, and loss of lock by the PLL.
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Reflects the state of the Copyright Channel Status bit in the incom-
CS8415A
31