CS8415A-IZ CIRRUS [Cirrus Logic], CS8415A-IZ Datasheet - Page 26

• Manufacturer Part Number: CS8415A-IZ
• Description: 96 kHz DIGITAL AUDIO INTERFACE RECEIVER
• Manufacturer: CIRRUS [Cirrus Logic]

will not affect the RERR pin, will not affect the RERR interrupt, and will not affect the current audio sample. The
CCRC and QCRC bits behave differently from the other bits: they do not affect the current audio sample even when
unmasked. This register defaults to 00h.
8.14
8.15
26
7
0
7
0
Channel Status Data Buffer Control (12h)
User Data Buffer Control (13h)
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
CBMR - Control for the first 5 bytes of channel status “E” buffer
DETCI - D to E C-data buffer transfer inhibit bit.
CAM - C-data buffer control port access mode bit
CHS - Channel select bit
DETUI - D to E U-data buffer transfer inhibit bit (valid in block mode only).
1 - Data buffer address space contains User data
1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data
1 - Inhibit C-data D to E buffer transfers
1 - Two byte mode
1 - Inhibit U-data D to E buffer transfers
Default = ‘0’
0 - Data buffer address space contains Channel Status data
Default = ‘0’
0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data
Default = ‘0’
0 - Allow C-data D to E buffer transfers
Default = ‘0’
0 - One byte mode
Default = ‘0’
0 - Channel A information is displayed at the EMPH pin and in the receiver channel status reg-
1 - Channel B information is displayed at the EMPH pin and in the receiver channel status reg-
Default = ‘0’
0 - Allow U-data D to E buffer transfers
6
6
0
0
ister. Channel A information is output during control port reads when CAM is set to 0 (One
Byte Mode)
ister. Channel B information is output during control port reads when CAM is set to 0 (One
Byte Mode)
BSEL
5
5
0
CBMR
4
4
0
DETCI
3
3
0
2
2
0
0
DETUI
CAM
1
1
CS8415A
CHS
0
0
0