CS8415A-IZ CIRRUS [Cirrus Logic], CS8415A-IZ Datasheet - Page 20

• Manufacturer Part Number: CS8415A-IZ
• Description: 96 kHz DIGITAL AUDIO INTERFACE RECEIVER
• Manufacturer: CIRRUS [Cirrus Logic]

8. CONTROL PORT REGISTER BIT DEFINITIONS
8.1
8.2
20
SWCLK
7
7
0
Control 1(01h)
Control 2 (02h)
SWCLK - Controls output of OMCK on RMCK when PLL loses lock
MUTESAO - Mute control for the serial audio output port
INT1:0 - Interrupt output pin (INT) control
HOLD1:0 - Determine how received audio sample is affected when a receiver error occurs
RMCKF - Select recovered master clock output pin frequency.
MMR - Select AES3 receiver mono or stereo operation
HOLD1
1 - OMCK output on RMCK pin
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
01 - Replace the current audio sample with 00 (mute)
10 - Do not change the received audio sample
11 - Reserved
1 - RMCK is equal to 128 * Fs
1 - A and B subframes treated as consecutive samples of one channel of data.
Default = ‘0’
0 - RMCK default function
Default = ‘0’
0 - Disabled
1 - Enabled
Default = ‘00’
00 - Active high; high output indicates interrupt condition has occurred
Default = ‘00’
00 - Hold the last valid audio sample
Default = ‘0’
0 - RMCK is equal to 256 * Fs
Default = ‘0’
0 - Normal stereo operation
6
6
0
Data is duplicated to both left and right parallel outputs of the AES receiver block.
The sample rate (Fs) is doubled compared to MMR=0
MUTESAO
HOLD0
5
5
RMCKF
4
4
0
MMR
3
0
3
MUX2
INT1
2
2
MUX1
INT0
1
1
CS8415A
MUX0
0
0
0