CS8420 CIRRUS [Cirrus Logic], CS8420 Datasheet - Page 31

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CS8420

Manufacturer Part Number
CS8420
Description
DIGITAL AUDIO SAMPLE RATE CONVERTER
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet

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11.3
TRUNC
MMR
MMT
MMTCS
MMTLR
DS245PP2
TRUNC
7
Miscellaneous Control 2 (2)
HOLD1-0The HOLD bits determine how the received audio sample is affected when a receiver
error occurs.
00 - Hold the last valid audio sample (default)
01 - Replace the current audio sample with 00 (mute)
10 - Do not change the received audio sample
11 - Reserved
RMCKFSelect recovered master clock output pin frequency.
0 - RMCK is equal to 256 * Fsi (default)
1 - RMCK is equal to 128 * Fsi
HOLD1
0 - Data to the SRC is not truncated (default)
1 - Data to the SRC is set according to the AUX field in the incoming data stream
0 - Interpret A and B subframes as two independent channels (normal stereo
1 - Interpret A and B subframes as consecutive samples of one channel of data.
0 - Outputs left channel input into A subframe and right channel input into B subframe
1 - Output either left or right channel inputs into consecutive subframe outputs (mono
0 - Use channel A CS data for the A sub-frame slot and use channel B CS data for the
1 - Use the same CS data for both the A and B sub-frame output slots. If MMTLR = 0, use the
0 - Use left channel input data for consecutive sub-frame outputs (default)
1- Use right channel input data for consecutive sub-frame outputs
Determines whether the word length is set according to the incoming Channel Status data
Select AES3 receiver mono or stereo operation
Select AES3 transmitter mono or stereo operation
Select A or B channel status data to transmit in mono mode
Channel Selection for AES Transmitter mono mode
6
This data is duplicated to both left and right parallel outputs of the AES receiver
block. The input sample rate (Fsi) is doubled compared to MMR=0
left channel CS data. If MMTLR = 1, use the right channel CS data.
operation, default)
(normal stereo operation, default).
mode, left or right is determined by MMTLR bit)
B sub-frame slot (default)
HOLD0
5
RMCKF
4
MMR
3
MMT
2
MMTCS
1
CS8420
MMTLR
0
31

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