CS8420 CIRRUS [Cirrus Logic], CS8420 Datasheet - Page 44

• Manufacturer Part Number: CS8420
• Description: DIGITAL AUDIO SAMPLE RATE CONVERTER
• Manufacturer: CIRRUS [Cirrus Logic]

12. SYSTEM AND APPLICATIONS
12.1 Reset, Power Down and Start-up
When RST is low, the CS8420 enters a low power
mode and all internal states are reset, including the
control port and registers, and the outputs are mut-
ed. When RST is high, the control port becomes
operational and the desired settings should be load-
ed into the control registers. Writing a 1 to the RUN
bit will then cause the part to leave the low power
state and begin operation. After the PLL and the
SRC have settled, the AES3 and serial audio out-
puts will be enabled.
Some options within the CS8420 are controlled by
a start-up mechanism. During the reset state, some
of the output pins are reconfigured internally to be
inputs. Immediately upon exiting the reset state, the
level of these pins is sensed. The pins are then
switched to be outputs. This mechanism allows
output pins to be used to set alternative modes in
the CS8420 by connecting a 47k
tween the pin and either VD+ (HI) or DGND (LO).
For each mode, every start-up option select pin
MUST have an external pull-up or pull-down resis-
tor. In software mode, the only start-up option pin
is EMPH, which is used to set a chip address bit for
the control port in I
many start-up options, which are detailed in the
hardware definition section at the end of this data
sheet.
12.2 ID Code and Revision Code
The CS8420 has a register that contains a 4-bit
code to indicate that the addressed device is a
CS8420. This is useful when other CS84XX family
members are resident in the same system, allowing
common software modules.
The CS8420 4-bit revision code is also available.
This allows the software driver for the CS8420 to
identify which revision of the device is in a partic-
44
ISSUES
Options
2
C mode. Hardware modes use
resistor to be-
ular system, and modify its behavior accordingly.
To allow for future revisions, it is strongly recom-
mend that the revision code is read into a variable
area within the microcontroller, and used wherever
appropriate as revision details become known.
12.3 Power Supply, Grounding, and PCB
For most applications, the CS8420 can be operated
from a single +5V supply, following normal supply
decoupling practice (see Figure 5. “Recommended
Connection Diagram for Software Mode” on page
10). For applications where the recovered input
clock, output on the RMCK pin, is required to be
low jitter, then use a separate, quiet, analog +5V
supply for VA+, decoupled to AGND. In addition,
a separate region of analog ground plane around the
FILT, AGND, VA+, RXP and RXN pins is recom-
mended.
The VD+ supply should be well decoupled with a
0.1 F capacitor to DGND to minimize AES3 trans-
mitter induced transients.
Extensive use of power and ground planes, ground
plane fill in unused areas and surface mount decou-
pling capacitors are recommended. Make sure de-
coupling capacitors are mounted on the same side
of the board as the CS8420, to minimize via induc-
tance effects. All decoupling capacitors should be
as close to the CS8420 as possible.
layout
CS8420
DS245PP2