CS8420 CIRRUS [Cirrus Logic], CS8420 Datasheet - Page 32

• Manufacturer Part Number: CS8420
• Description: DIGITAL AUDIO SAMPLE RATE CONVERTER
• Manufacturer: CIRRUS [Cirrus Logic]

11.4
AMLL
TXOFF
AESBP
TXD1 - TXD0
SPD1 - SPD0
SRCD
32
AMLL
7
Data Flow Control (3)
The Data Flow Control register configures the flow of audio data to/from the following blocks: Serial
Audio Input Port, Serial Audio Output Port, AES3 receiver, AES3 transmitter, and Sample Rate Con-
verter. In conjunction with the Clock Source Control register, multiple Receiver/Transmitter/Trans-
ceiver modes may be selected. The output data should be muted prior to changing bits in this register
to avoid transients.
TXOFF
data sink may be either, or both, the Transmitter and the Serial Audio Output Port.
0 - Disables Auto Mute on loss of lock (default)
1 - Enables Auto Mute on loss of lock
0 - AES3 transmitter output pin drivers normal operation (default)
1 - AES3 transmitter output pin drivers drive to 0V.
0 - normal operation
1 - Connect the AES3 transmitter driver input directly to the RXP pin, which become
00 - SRC output (default)
01 - Serial audio input port
10 - AES3 receiver
11 - Reserved
00 - SRC output (default)
01 - Serial Audio Input Port
10 - AES3 receiver
11 - Reserved
0 - Serial Audio Input Port (default)
1 - AES3 Receiver
Auto Mutes the SRC data sink when Receiver lock is lost, zero data is transmitted. The SRC
AES3 Transmitter Output Driver Control
AES3 bypass mode selection
AES3 Transmitter Data Source
Serial Audio Output Port Data Source
Input Data Source for SRC
6
a normal TTL threshold digital input.
AESBP
5
TXD1
4
TXD0
3
SPD1
2
SPD0
1
CS8420
DS245PP2
SRCD
0