CS8420 CIRRUS [Cirrus Logic], CS8420 Datasheet - Page 56

• Manufacturer Part Number: CS8420
• Description: DIGITAL AUDIO SAMPLE RATE CONVERTER
• Manufacturer: CIRRUS [Cirrus Logic]

14.4 Hardware Mode 3 Description
(Transceive Data Flow, with SRC)
Hardware Mode 3 data flow is shown in Figure 28.
Audio data is input via the AES3 receiver, and rate
converted. The audio data at the new rate is then
output via the serial audio output port. Different au-
dio data, synchronous to OMCK, may be input into
the serial audio input port, and output via the AES3
transmitter.
The channel status data, user data and validity bit
information are handled in 2 alternative modes: 3A
and 3B, determined by a start-up resistor on the
COPY pin. In mode 3A, the received PRO, COPY,
ORIG, and AUDIO channel status bits are output
on pins. The transmitted channel status bits are
copied from the received channel status data, and
the transmitted U and V bits are 0.
56
RXP
RXN
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
RMCK RERR
VD+
Figure 28. Hardware Mode 3 - Transceive Data Flow, with SRC
DFC0
Clocked by
Input Derived Clock
AES3 Rx
&
Decoder
DFC1
VD+
Sample
Rate
Converter
H/S
Clocked by
Output Clock
PRO/C
SDOUT
OSCLK
Serial
Audio
Output
COPY ORIG EMPH/U AUDIO/V TCBL
OLRCK
C & U bit Data Buffer
In mode 3B, only the COPY and ORIG pins are
output, and reflect the received channel status data.
The transmitted channel status bits, user data and
validity bits are input serially via the PRO/C, EM-
PH/U and AUDIO/V pins. Figure 22 shows the
timing requirements.
The serial audio input port is always a slave.
If a validity, parity, bi-phase or lock receiver error
occurs, the current audio sample will be held.
Start-up options are shown in Table 10, and allow
choice of the serial audio output port as a master or
slave, whether TCBL is an input or an output, the
serial audio ports formats and the source of the
transmitted C, U and V data.
The following pages contain the detailed pin de-
scriptions for hardware mode 3.
ILRCK
ISCLK
Serial
Audio
Input
SDIN
AES3
Encoder
& Tx
Output
Clock
Source
OMCK
TXP
TXN
CS8420
DS245PP2