M58WR032FB60ZB6 STMICROELECTRONICS [STMicroelectronics], M58WR032FB60ZB6 Datasheet - Page 16

• Manufacturer Part Number: M58WR032FB60ZB6
• Description: 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58WR032FT, M58WR032FB
ation, start a programming operation, suspend the
programming operation then read the array. See
APPENDIX
Resume Flowchart and Pseudo
27., Erase Suspend & Resume Flowchart and
Pseudo
gram/Erase Resume command.
Protection Register Program Command
The Protection Register Program command is
used to Program the 128 bit user One-Time-Pro-
grammable (OTP) segment of the Protection Reg-
ister and the Protection Register Lock. The
segment is programmed 16 bits at a time. When
shipped all bits in the segment are set to ‘1’. The
user can only program the bits to ‘0’.
Two write cycles are required to issue the Protec-
tion Register Program command.
Read operations output the Status Register con-
tent after the programming has started.
The segment can be protected by programming bit
1 of the Protection Lock Register (see
Protection Register Memory
program a previously protected Protection Regis-
ter will result in a Status Register error. The pro-
tection of the Protection Register is not reversible.
The Protection Register Program cannot be sus-
pended. See
tion Register Program Flowchart and Pseudo
Code, for a flowchart for using the Protection Reg-
ister Program command.
Set Configuration Register Command
The Set Configuration Register command is used
to write a new value to the Configuration Register
which defines the burst length, type, X latency,
Synchronous/Asynchronous Read mode and the
valid Clock edge configuration.
Two Bus Write cycles are required to issue the Set
Configuration Register command.
Read operations output the memory array content
after the Set Configuration Register command is
issued.
The value for the Configuration Register is always
presented on A0-A15. CR0 is on A0, CR1 on A1,
etc.; the other address bits are ignored.
16/86
The first bus cycle sets up the Protection
Register Program command.
The second latches the Address and the Data
to be written to the Protection Register and
starts the Program/Erase Controller.
The first cycle writes the setup command and
the address corresponding to the
Configuration Register content.
The second cycle writes the Configuration
Register data and the confirm command.
Code, for flowcharts for using the Pro-
C.,
APPENDIX
Figure 25., Program Suspend &
C.,
Map). Attempting to
Figure 29., Protec-
Code, and
Figure 5.,
Figure
Block Lock Command
The Block Lock command is used to lock a block
and prevent Program or Erase operations from
changing the data in it. All blocks are locked at
power-up or reset.
Two Bus Write cycles are required to issue the
Block Lock command.
The lock status can be monitored for each block
using the Read Electronic Signature command. .
Table 13.
Block Lock command.
The Block Lock bits are volatile, once set they re-
main set until a hardware reset or power-down/
power-up. They are cleared by a Block Unlock
command. Refer to the section,
ING, for a detailed explanation. See
C.,
Pseudo
command.
Block Unlock Command
The Block Unlock command is used to unlock a
block, allowing the block to be programmed or
erased. Two Bus Write cycles are required to is-
sue the Block Unlock command.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table 13.
a Block Unlock command. Refer to the section,
BLOCK
APPENDIX
Flowchart and Pseudo
using the Unlock command.
Block Lock-Down Command
A locked or unlocked block can be locked-down by
issuing the Block Lock-Down command. A locked-
down block cannot be programmed or erased, or
have its protection status changed when WP is
low, V
function is disabled and the locked blocks can be
individually unlocked by the Block Unlock com-
mand.
Two Bus Write cycles are required to issue the
Block Lock-Down command.
Figure 28., Locking Operations Flowchart and
The first bus cycle sets up the Block Lock
command.
The second Bus Write cycle latches the block
address.
The first bus cycle sets up the Block Unlock
command.
The second Bus Write cycle latches the block
address.
The first bus cycle sets up the Block Lock
command.
The second Bus Write cycle latches the block
address.
IL
. When WP is high, V
LOCKING, for a detailed explanation and
Code, for a flowchart for using the Lock
shows the protection status after issuing
shows the Lock Status after issuing a
C.,
Figure 28., Locking Operations
Code, for a flowchart for
IH,
BLOCK LOCK-
the Lock-Down
APPENDIX