M58WR032FB60ZB6 STMICROELECTRONICS [STMicroelectronics], M58WR032FB60ZB6 Datasheet - Page 27

• Manufacturer Part Number: M58WR032FB60ZB6
• Description: 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

(no wrap). The Wrap Burst bit is used to select be-
tween wrap and no wrap. When the Wrap Burst bit
is set to ‘0’ the burst read wraps; when it is set to
‘1’ the burst read does not wrap.
Burst length Bits (CR2-CR0)
The Burst Length bits set the number of Words to
be output during a Synchronous Burst Read oper-
ation as result of a single address latch cycle.
They can be set for 4 Words, 8 Words, 16 Words
or continuous burst, where all the words are read
sequentially.
In continuous burst mode the burst sequence can
cross bank boundaries.
In continuous burst mode or in 4, 8, 16 Words no-
wrap, depending on the starting address, the de-
Table 9. Configuration Register
CR13-CR11
CR5-CR4
CR2-CR0
CR15
CR14
CR10
CR9
CR8
CR7
CR6
CR3
Bit
Read Select
Reserved
Wait Polarity
Data Output
Configuration
Wait Configuration
Burst Type
Valid Clock Edge
Reserved
Wrap Burst
Burst Length
X-Latency
Description
0
1
010
011
100
101
111
Other configurations reserved
0
1
0
1
0
1
0
1
0
1
0
1
001
010
011
111
Value
Synchronous Read
Asynchronous Read (Default at power-on)
2 clock latency
3 clock latency
4 clock latency
5 clock latency
Reserved (default)
WAIT is active Low
WAIT is active high (default)
Data held for one clock cycle
Data held for two clock cycles (default)
WAIT is active one data cycle before wait state (default)
Interleaved
Sequential (default)
Falling Clock edge
Rising Clock edge (default)
Wrap
No Wrap (default)
4 Words
8 Words
16 Words
Continuous (CR7 must be set to ‘1’) (default)
WAIT is active during wait state
vice asserts the WAIT output to indicate that a de-
lay is necessary before the data is output.
If the starting address is aligned to a 4 Word
boundary no wait states are needed and the WAIT
output is not asserted.
If the starting address is shifted by 1,2 or 3 posi-
tions from the four word boundary, WAIT will be
asserted for 1, 2 or 3 clock cycles when the burst
sequence crosses the first 16 Word boundary, to
indicate that the device needs an internal delay to
read the successive words in the array. WAIT will
be asserted only once during a continuous burst
access. See also
CR14, CR5 and CR4 are reserved for future use.
M58WR032FT, M58WR032FB
Description
Table 10., Burst Type
Definition.
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