STM8S105C4B3 STMICROELECTRONICS [STMicroelectronics], STM8S105C4B3 Datasheet - Page 102

• Manufacturer Part Number: STM8S105C4B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Electrical characteristics
10.3.12
10.3.12.1
10.3.12.2
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EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
•
•
A device reset allows normal operations to be resumed. The test results are given in the table
below based on the EMS levels and classes defined in application note AN1709 (EMC design
guide for STMicrocontrollers).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques
for improving microcontroller EMC performance).
E
point correlation line.
FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of
the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to V
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with
the IEC 61000-4-4 standard.
L
= Integral linearity error: maximum deviation between any actual transition and the end
V AIN
R AIN
C AIN
Figure 46: Typical application with ADC
AINx
DocID14771 Rev 9
V DD
V T
0.6 V
V T
0.6 V
I L
± 1 µA
conversion
10-bit A/D
STM8S105xx
DD
STM8
C ADC
and V
SS