STM8S105C4B3 STMICROELECTRONICS [STMicroelectronics], STM8S105C4B3 Datasheet - Page 11

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STM8S105C4B3

Manufacturer Part Number
STM8S105C4B3
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
STM8S105xx
3
Up to 10 channels
Block diagram
Master/slave
autosynchro
LIN master
SPI emul.
Single wire
debug interf.
400 Kbit/s
1/2/4 kHz
beep
8 Mbit/s
Reset
Figure 1: STM8S105xx access line block diagram
POR
Debug/SWIM
STM8 core
Reset block
UART2
Beeper
Reset
ADC1
I
SPI
2
C
BOR
Clock to peripherals and core
DocID14771 Rev 9
Clock controller
Detector
16-bit advanced control
16-bit general purpose
timers (TIM2, TIM3)
Independent WDG
Up to 32 Kbytes
XTAL 1-16 MHz
8-bit basic timer
data EEPROM
RC int. 128 kHz
Up to 2 Kbytes
RC int. 16 MHz
Window WDG
program Flash
timer (TIM1)
Boot ROM
AWU timer
1 Kbytes
(TIM4)
RAM
Up to
5 CAPCOM
channels
Up to
4 CAPCOM
channels +3
complementary
outputs
Block diagram
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