FAN53168MTC FAIRCHILD [Fairchild Semiconductor], FAN53168MTC Datasheet - Page 20

• Manufacturer Part Number: FAN53168MTC
• Description: 6-Bit VID Controlled 2-4 Phase DC-DC Controller
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

FAN53168
capacitors must be increased. One should note for this multi-
mode control technique, “all-ceramic” designs can be used
as long as the conditions of Equations 11, 12 and 13 are
satisfied.
Power MOSFETs
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches
per phase. The main selection parameters for the power
MOSFETs are V
The minimum gate drive voltage (the supply voltage to the
FAN53418) dictates whether standard threshold or logic-
level threshold MOSFETs must be used. With V
logic-level threshold MOSFETs (V
recommended. The maximum output current I
the R
MOSFETs. With the FAN53168, currents are balanced
between phases, thus the current in each low-side MOSFET
is the output current divided by the total number of
MOSFETs (n
the following expression shows the total power being
dissipated in each synchronous MOSFET in terms of the
ripple current per phase (I
(I
Knowing the maximum output current being designed for
and the maximum allowed power dissipation, one can find
the required R
MOSFETs up to an ambient temperature of 50°C, a safe
limit for P
Thus, for our example (65A maximum), we find R
(per MOSFET) < 8.7mΩ. This R
temperature of about 125°C, so we need to make sure we
account for this when making this selection. For our
example, we selected two lower side MOSFETs at 8.6mΩ
each at room temperature, which gives 8.4mΩ at high
temperature.
Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio of
the feedback to input needs to be small (less than 10% is
recommended) to prevent accidental turn-on of the synchro-
nous MOSFETs when the switch node goes high.
20
P
O
SF
):
DS(ON)
=
(
1 D
–
SF
requirement for the low-side (synchronous)
is 1W-1.5W at 125°C junction temperature.
SF
)
DS(ON)
×
). With conduction losses being dominant,
GS(TH)


---------
n
I
SF
O
for the MOSFET. For D-PAK


, Q
2
+
R
G
) and average total output current
----- -
12
1
, C
×
ISS


DS(SF)
n I
--------------
n
, C
×
GS(TH)
SF
RSS
R


is also at a junction
2
Ω
and R
< 2.5V) are
×
Ω
R
DS SF
O
DS(ON)
GATE
determines
Ω
(
DS(SF)
)
~10V,
.
The high-side (main) MOSFET has to be able to handle two
main power dissipation components; conduction and switch-
ing losses. The switching loss is related to the amount of
time it takes for the main MOSFET to turn on and off, and to
the current and voltage that are being switched. Basing the
switching speed on the rise and fall time of the gate driver
impedance and MOSFET input capacitance, the following
expression provides an approximate value for the switching
loss per main MOSFET, where n
main MOSFETs:
P
The conduction loss of the main MOSFET is given by the
following, where R
MOSFET:
Typically, for main MOSFETs, one wants the highest speed
(low C
tance. One must select a device that meets the total power
dissipation (about 1.5 W for a single D-PAK) when combin-
ing the switching and conduction losses.
One last thing to look at is the power dissipation in the driver
for each phase. This is best described in terms of the Q
the MOSFETs and is given by the following, where Q
the total gate charge for each main MOSFET and Q
total gate charge for each synchronous MOSFET:
P
P
S MF
C MF
DRV
(
(
)
)
ISS
=
=
=
) device, but these usually have higher ON-resis-
------------
2 n
2 f
D
f
Ω
SW
×
×
×
SW
Ω
×


--------- -
n
(
I
MF
×
n
O
DS(MF)
MF
V
---------------------- -


CC
2
n
×
+
MF
Q
×
----- -
12
1
Ω
is the ON-resistance of the
GMF
I
O
×
×


R
n I
--------------
+
n
MF
G
×
n
MF
SF
PRODUCT SPECIFICATION
×
R
is the total number of
n
--------- -


×
MF
n
Ω
2
Q
×
GSF
×
R
REV. 1.0.0 6/9/03
C
DS MF
ISS
)
+
(
I
CC
)
GSF
×
GMF
G
is the
V
CC
Ω
for
is