ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet - Page 15

• Manufacturer Part Number: ATTINY15
• Manufacturer: ATMEL [ATMEL Corporation]

Power-on Reset
1187D–12/01
Table 6. Number of Watchdog Oscillator Cycles
A Power-on Reset (POR) pulse is generated by an On-chip Detection circuit. The detec-
tion level is nominally defined in Table 4. The POR is activated whenever V
the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reach-
ing the Power-on Reset threshold voltage invokes a delay counter, which determines
the delay, for which the device is kept in RESET after V
the delay counter can be defined by the user through the CKSEL fuses. The different
selections for the delay period are presented in Table 5. The RESET signal is activated
again, without any delay, when the V
Figure 13. “MCU Start-up, RESET Tied to V
INTERNAL
TIME-OUT
RESET
RESET
VCC
V
CC
Conditions
2.7V
2.7V
2.7V
2.7V
5.0V
5.0V
5.0V
5.0V
V
V
POT
RST
t
TOUT
CC
Time-out
256 ms
128 µs
16 ms
64 ms
32 µs
32 µs
4 ms
8 µs
decreases below detection level.
CC
CC
rise. The time-out period of
Number of Cycles
64K
64K
ATtiny15L
4K
4K
32
32
8
8
CC
is below
15